| 24 | } |
| 25 | |
| 26 | pub fn compile<C: Config, I: InputType>( |
| 27 | rc: &ir::dest::RootCircuit<C>, |
| 28 | opts: CompileOptions, |
| 29 | ) -> (layered::Circuit<C, I>, InputMapping) { |
| 30 | let mut ctx = compile::CompileContext { |
| 31 | rc, |
| 32 | circuits: HashMap::new(), |
| 33 | order: Vec::new(), |
| 34 | layer_layout_pool: Pool::new(), |
| 35 | layer_req_to_layout: HashMap::new(), |
| 36 | compiled_circuits: Vec::new(), |
| 37 | conncected_wires: HashMap::new(), |
| 38 | layout_ids: Vec::new(), |
| 39 | layers: Vec::new(), |
| 40 | input_order: Vec::new(), |
| 41 | root_has_constraints: false, |
| 42 | opts, |
| 43 | }; |
| 44 | ctx.compile(); |
| 45 | let t: &I::InputUsize = &ctx.compiled_circuits[ctx.layers[0]].num_inputs; |
| 46 | let l0_size = t.get(0); |
| 47 | let output_zeroes = rc.expected_num_output_zeroes + ctx.root_has_constraints as usize; |
| 48 | let output_all = rc.circuits[&0].outputs.len() + ctx.root_has_constraints as usize; |
| 49 | ( |
| 50 | layered::Circuit { |
| 51 | num_public_inputs: rc.num_public_inputs, |
| 52 | num_actual_outputs: output_all, |
| 53 | expected_num_output_zeroes: output_zeroes, |
| 54 | segments: ctx.compiled_circuits, |
| 55 | layer_ids: ctx.layers, |
| 56 | }, |
| 57 | InputMapping::new(l0_size, ctx.input_order), |
| 58 | ) |
| 59 | } |