| 1342 | } |
| 1343 | |
| 1344 | u64 MipsExpressionFunctions::getReferenceValue(u64 referenceIndex) |
| 1345 | { |
| 1346 | if (referenceIndex < 32) |
| 1347 | return m_cpu->getRegister(0, referenceIndex)._u64[0]; |
| 1348 | if (referenceIndex == REF_INDEX_PC) |
| 1349 | return m_cpu->getPC(); |
| 1350 | if (referenceIndex == REF_INDEX_HI) |
| 1351 | return m_cpu->getHI()._u64[0]; |
| 1352 | if (referenceIndex == REF_INDEX_LO) |
| 1353 | return m_cpu->getLO()._u64[0]; |
| 1354 | if (referenceIndex & REF_INDEX_IS_OPSL) |
| 1355 | { |
| 1356 | const u32 OP = m_cpu->Read32(m_cpu->getPC()); |
| 1357 | const R5900::OPCODE& opcode = R5900::GetInstruction(OP); |
| 1358 | if (opcode.flags & IS_MEMORY) |
| 1359 | { |
| 1360 | // Fetch the address in the base register |
| 1361 | u32 target = cpuRegs.GPR.r[(OP >> 21) & 0x1F].UD[0]; |
| 1362 | // Add the offset (lower 16 bits) |
| 1363 | target += static_cast<u16>(OP); |
| 1364 | |
| 1365 | if (referenceIndex & REF_INDEX_OPTARGET) |
| 1366 | { |
| 1367 | return target; |
| 1368 | } |
| 1369 | else if (referenceIndex & REF_INDEX_OPLOAD) |
| 1370 | { |
| 1371 | return (opcode.flags & IS_LOAD) ? target : 0; |
| 1372 | } |
| 1373 | else if (referenceIndex & REF_INDEX_OPSTORE) |
| 1374 | { |
| 1375 | return (opcode.flags & IS_STORE) ? target : 0; |
| 1376 | } |
| 1377 | } |
| 1378 | return 0; |
| 1379 | } |
| 1380 | if (referenceIndex & REF_INDEX_FPU) |
| 1381 | { |
| 1382 | return m_cpu->getRegister(EECAT_FPR, referenceIndex & 0x1F)._u64[0]; |
| 1383 | } |
| 1384 | return -1; |
| 1385 | } |
| 1386 | |
| 1387 | ExpressionType MipsExpressionFunctions::getReferenceType(u64 referenceIndex) |
| 1388 | { |
no test coverage detected