| 414 | } |
| 415 | |
| 416 | void _dmaSPR1() // toSPR work function |
| 417 | { |
| 418 | switch(spr1ch.chcr.MOD) |
| 419 | { |
| 420 | case NORMAL_MODE: |
| 421 | { |
| 422 | //int cycles = 0; |
| 423 | // Transfer Dn_QWC from Dn_MADR to SPR1 |
| 424 | SPR1chain(); |
| 425 | spr1finished = true; |
| 426 | return; |
| 427 | } |
| 428 | case CHAIN_MODE: |
| 429 | { |
| 430 | tDMA_TAG *ptag; |
| 431 | bool done = false; |
| 432 | |
| 433 | if (spr1ch.qwc > 0) |
| 434 | { |
| 435 | SPR_LOG("spr1 Normal or in Progress size=%d, addr=%lx taddr=%lx saddr=%lx", spr1ch.qwc, spr1ch.madr, spr1ch.tadr, spr1ch.sadr); |
| 436 | // Transfer Dn_QWC from Dn_MADR to SPR1 |
| 437 | SPR1chain(); |
| 438 | return; |
| 439 | } |
| 440 | // Chain Mode |
| 441 | |
| 442 | ptag = SPRdmaGetAddr(spr1ch.tadr, false); // Set memory pointer to TADR |
| 443 | |
| 444 | if (!spr1ch.transfer("SPR1 Tag", ptag)) |
| 445 | { |
| 446 | done = true; |
| 447 | spr1finished = done; |
| 448 | } |
| 449 | |
| 450 | spr1ch.madr = ptag[1]._u32; // MADR = ADDR field + SPR |
| 451 | |
| 452 | // Transfer dma tag if tte is set |
| 453 | if (spr1ch.chcr.TTE) |
| 454 | { |
| 455 | SPR_LOG("SPR TTE: %x_%x\n", ptag[3]._u32, ptag[2]._u32); |
| 456 | SPR1transfer(ptag, 1); // Transfer Tag |
| 457 | } |
| 458 | |
| 459 | SPR_LOG("spr1 dmaChain %8.8x_%8.8x size=%d, id=%d, addr=%lx taddr=%lx saddr=%lx", |
| 460 | ptag[1]._u32, ptag[0]._u32, spr1ch.qwc, ptag->ID, spr1ch.madr, spr1ch.tadr, spr1ch.sadr); |
| 461 | |
| 462 | done = hwDmacSrcChain(spr1ch, ptag->ID); |
| 463 | SPR1chain(); // Transfers the data set by the switch |
| 464 | |
| 465 | if (spr1ch.chcr.TIE && ptag->IRQ) // Check TIE bit of CHCR and IRQ bit of tag |
| 466 | { |
| 467 | SPR_LOG("dmaIrq Set"); |
| 468 | |
| 469 | //Console.WriteLn("SPR1 TIE"); |
| 470 | done = true; |
| 471 | } |
| 472 | |
| 473 | spr1finished = done; |
no test coverage detected