| 389 | } |
| 390 | |
| 391 | void _SPR1interleave() |
| 392 | { |
| 393 | int qwc = spr1ch.qwc; |
| 394 | int tqwc = dmacRegs.sqwc.TQWC; |
| 395 | const int sqwc = dmacRegs.sqwc.SQWC; |
| 396 | tDMA_TAG *pMem; |
| 397 | |
| 398 | if (tqwc == 0) tqwc = qwc; |
| 399 | SPR_LOG("SPR1 interleave size=%d, tqwc=%d, sqwc=%d, addr=%lx sadr=%lx", |
| 400 | spr1ch.qwc, tqwc, sqwc, spr1ch.madr, spr1ch.sadr); |
| 401 | CPU_INT(DMAC_TO_SPR, qwc * BIAS); |
| 402 | while (qwc > 0) |
| 403 | { |
| 404 | spr1ch.qwc = std::min(tqwc, qwc); |
| 405 | qwc -= spr1ch.qwc; |
| 406 | pMem = SPRdmaGetAddr(spr1ch.madr, false); |
| 407 | memcpy_to_spr(spr1ch.sadr, (u8*)pMem, spr1ch.qwc*16); |
| 408 | spr1ch.sadr += spr1ch.qwc * 16; |
| 409 | spr1ch.sadr &= 0x3FFF; // Limited to 16K |
| 410 | spr1ch.madr += (sqwc + spr1ch.qwc) * 16; |
| 411 | } |
| 412 | |
| 413 | spr1ch.qwc = 0; |
| 414 | } |
| 415 | |
| 416 | void _dmaSPR1() // toSPR work function |
| 417 | { |
no test coverage detected