| 92 | } |
| 93 | |
| 94 | __ri void cpuException(u32 code, u32 bd) |
| 95 | { |
| 96 | bool errLevel2, checkStatus; |
| 97 | u32 offset = 0; |
| 98 | |
| 99 | cpuRegs.branch = 0; // Tells the interpreter that an exception occurred during a branch. |
| 100 | cpuRegs.CP0.n.Cause = code & 0xffff; |
| 101 | |
| 102 | if(cpuRegs.CP0.n.Status.b.ERL == 0) |
| 103 | { |
| 104 | //Error Level 0-1 |
| 105 | errLevel2 = false; |
| 106 | checkStatus = (cpuRegs.CP0.n.Status.b.BEV == 0); // for TLB/general exceptions |
| 107 | |
| 108 | if (((code & 0x7C) >= 0x8) && ((code & 0x7C) <= 0xC)) |
| 109 | offset = 0x0; //TLB Refill |
| 110 | else if ((code & 0x7C) == 0x0) |
| 111 | offset = 0x200; //Interrupt |
| 112 | else |
| 113 | offset = 0x180; // Everything else |
| 114 | } |
| 115 | else |
| 116 | { |
| 117 | //Error Level 2 |
| 118 | errLevel2 = true; |
| 119 | checkStatus = (cpuRegs.CP0.n.Status.b.DEV == 0); // for perf/debug exceptions |
| 120 | |
| 121 | Console.Error("*PCSX2* FIX ME: Level 2 cpuException"); |
| 122 | if ((code & 0x38000) <= 0x8000 ) |
| 123 | { |
| 124 | //Reset / NMI |
| 125 | cpuRegs.pc = 0xBFC00000; |
| 126 | Console.Warning("Reset request"); |
| 127 | cpuUpdateOperationMode(); |
| 128 | return; |
| 129 | } |
| 130 | else if ((code & 0x38000) == 0x10000) |
| 131 | offset = 0x80; //Performance Counter |
| 132 | else if ((code & 0x38000) == 0x18000) |
| 133 | offset = 0x100; //Debug |
| 134 | else |
| 135 | Console.Error("Unknown Level 2 Exception!! Cause %x", code); |
| 136 | } |
| 137 | |
| 138 | if (cpuRegs.CP0.n.Status.b.EXL == 0) |
| 139 | { |
| 140 | cpuRegs.CP0.n.Status.b.EXL = 1; |
| 141 | if (bd) |
| 142 | { |
| 143 | Console.Warning("branch delay!!"); |
| 144 | cpuRegs.CP0.n.EPC = cpuRegs.pc - 4; |
| 145 | cpuRegs.CP0.n.Cause |= 0x80000000; |
| 146 | } |
| 147 | else |
| 148 | { |
| 149 | cpuRegs.CP0.n.EPC = cpuRegs.pc; |
| 150 | cpuRegs.CP0.n.Cause &= ~0x80000000; |
| 151 | } |
no test coverage detected