| 316 | } |
| 317 | |
| 318 | static __fi void _cpuTestTIMR() |
| 319 | { |
| 320 | cpuRegs.CP0.n.Count += cpuRegs.cycle - cpuRegs.lastCOP0Cycle; |
| 321 | cpuRegs.lastCOP0Cycle = cpuRegs.cycle; |
| 322 | |
| 323 | // fixme: this looks like a hack to make up for the fact that the TIMR |
| 324 | // doesn't yet have a proper mechanism for setting itself up on a nextEventCycle. |
| 325 | // A proper fix would schedule the TIMR to trigger at a specific cycle anytime |
| 326 | // the Count or Compare registers are modified. |
| 327 | |
| 328 | if ( (cpuRegs.CP0.n.Status.val & 0x8000) && |
| 329 | cpuRegs.CP0.n.Count >= cpuRegs.CP0.n.Compare && cpuRegs.CP0.n.Count < cpuRegs.CP0.n.Compare+1000 ) |
| 330 | { |
| 331 | Console.WriteLn( Color_Magenta, "timr intr: %x, %x", cpuRegs.CP0.n.Count, cpuRegs.CP0.n.Compare); |
| 332 | cpuException(0x808000, cpuRegs.branch); |
| 333 | } |
| 334 | } |
| 335 | |
| 336 | static __fi void _cpuTestPERF() |
| 337 | { |
no test coverage detected