| 92 | } |
| 93 | |
| 94 | __fi void gsWrite8(u32 mem, u8 value) |
| 95 | { |
| 96 | switch (mem) |
| 97 | { |
| 98 | // CSR 8-bit write handlers. |
| 99 | // I'm quite sure these would just write the CSR portion with the other |
| 100 | // bits set to 0 (no action). The previous implementation masked the 8-bit |
| 101 | // write value against the previous CSR write value, but that really doesn't |
| 102 | // make any sense, given that the real hardware's CSR circuit probably has no |
| 103 | // real "memory" where it saves anything. (for example, you can't write to |
| 104 | // and change the GS revision or ID portions -- they're all hard wired.) --air |
| 105 | |
| 106 | case GS_CSR: // GS_CSR |
| 107 | gsCSRwrite( tGS_CSR((u32)value) ); break; |
| 108 | case GS_CSR + 1: // GS_CSR |
| 109 | gsCSRwrite( tGS_CSR(((u32)value) << 8) ); break; |
| 110 | case GS_CSR + 2: // GS_CSR |
| 111 | gsCSRwrite( tGS_CSR(((u32)value) << 16) ); break; |
| 112 | case GS_CSR + 3: // GS_CSR |
| 113 | gsCSRwrite( tGS_CSR(((u32)value) << 24) ); break; |
| 114 | |
| 115 | default: |
| 116 | *PS2GS_BASE(mem) = value; |
| 117 | break; |
| 118 | } |
| 119 | GIF_LOG("GS write 8 at %8.8lx with data %8.8lx", mem, value); |
| 120 | } |
| 121 | |
| 122 | ////////////////////////////////////////////////////////////////////////// |
| 123 | // GS Write 16 bit |
no test coverage detected