| 29 | } |
| 30 | |
| 31 | static __fi void gsCSRwrite( const tGS_CSR& csr ) |
| 32 | { |
| 33 | if (csr.RESET) { |
| 34 | GUNIT_WARN("GUNIT_WARN: csr.RESET"); |
| 35 | //Console.Warning( "csr.RESET" ); |
| 36 | //gifUnit.Reset(true); // Don't think gif should be reset... |
| 37 | gifUnit.gsSIGNAL.queued = false; |
| 38 | gifUnit.gsFINISH.gsFINISHFired = true; |
| 39 | gifUnit.gsFINISH.gsFINISHPending = false; |
| 40 | // Privilage registers also reset. |
| 41 | std::memset(g_RealGSMem, 0, sizeof(g_RealGSMem)); |
| 42 | GSIMR.reset(); |
| 43 | CSRreg.Reset(); |
| 44 | MTGS::ResetGS(false); |
| 45 | } |
| 46 | |
| 47 | if(csr.FLUSH) |
| 48 | { |
| 49 | // Our emulated GS has no FIFO, but if it did, it would flush it here... |
| 50 | //Console.WriteLn("GS_CSR FLUSH GS fifo: %x (CSRr=%x)", value, GSCSRr); |
| 51 | } |
| 52 | |
| 53 | if(csr.SIGNAL) |
| 54 | { |
| 55 | const bool resume = CSRreg.SIGNAL; |
| 56 | // SIGNAL : What's not known here is whether or not the SIGID register should be updated |
| 57 | // here or when the IMR is cleared (below). |
| 58 | GUNIT_LOG("csr.SIGNAL"); |
| 59 | if (gifUnit.gsSIGNAL.queued) { |
| 60 | //DevCon.Warning("Firing pending signal"); |
| 61 | GSSIGLBLID.SIGID = (GSSIGLBLID.SIGID & ~gifUnit.gsSIGNAL.data[1]) |
| 62 | | (gifUnit.gsSIGNAL.data[0]&gifUnit.gsSIGNAL.data[1]); |
| 63 | |
| 64 | if (!GSIMR.SIGMSK) gsIrq(); |
| 65 | CSRreg.SIGNAL = true; // Just to be sure :p |
| 66 | } |
| 67 | else CSRreg.SIGNAL = false; |
| 68 | gifUnit.gsSIGNAL.queued = false; |
| 69 | |
| 70 | if (resume) |
| 71 | gifUnit.Execute(false, true); // Resume paused transfers |
| 72 | } |
| 73 | |
| 74 | if (csr.FINISH) { |
| 75 | CSRreg.FINISH = false; |
| 76 | gifUnit.gsFINISH.gsFINISHFired = false; //Clear the previously fired FINISH (YS, Indiecar 2005, MGS3) |
| 77 | gifUnit.gsFINISH.gsFINISHPending = false; |
| 78 | } |
| 79 | if(csr.HSINT) CSRreg.HSINT = false; |
| 80 | if(csr.VSINT) CSRreg.VSINT = false; |
| 81 | if(csr.EDWINT) CSRreg.EDWINT = false; |
| 82 | } |
| 83 | |
| 84 | static __fi void IMRwrite(u32 value) |
| 85 | { |
no test coverage detected