---------- write a OPL registers ---------- */
| 750 | |
| 751 | /* ---------- write a OPL registers ---------- */ |
| 752 | static void OPLWriteReg(FM_OPL *OPL, int r, int v) |
| 753 | { |
| 754 | OPL_CH *CH; |
| 755 | int slot; |
| 756 | int block_fnum; |
| 757 | |
| 758 | switch(r&0xe0) |
| 759 | { |
| 760 | case 0x00: /* 00-1f:control */ |
| 761 | switch(r&0x1f) |
| 762 | { |
| 763 | case 0x01: |
| 764 | /* wave selector enable */ |
| 765 | if(OPL->type&OPL_TYPE_WAVESEL) |
| 766 | { |
| 767 | OPL->wavesel = v&0x20; |
| 768 | if(!OPL->wavesel) |
| 769 | { |
| 770 | /* preset compatible mode */ |
| 771 | int c; |
| 772 | for(c=0;c<OPL->max_ch;c++) |
| 773 | { |
| 774 | OPL->P_CH[c].SLOT[SLOT1].wavetable = &SIN_TABLE[0]; |
| 775 | OPL->P_CH[c].SLOT[SLOT2].wavetable = &SIN_TABLE[0]; |
| 776 | } |
| 777 | } |
| 778 | } |
| 779 | return; |
| 780 | case 0x02: /* Timer 1 */ |
| 781 | OPL->T[0] = (256-v)*4; |
| 782 | break; |
| 783 | case 0x03: /* Timer 2 */ |
| 784 | OPL->T[1] = (256-v)*16; |
| 785 | return; |
| 786 | case 0x04: /* IRQ clear / mask and Timer enable */ |
| 787 | if(v&0x80) |
| 788 | { /* IRQ flag clear */ |
| 789 | OPL_STATUS_RESET(OPL,0x7f); |
| 790 | } |
| 791 | else |
| 792 | { /* set IRQ mask ,timer enable*/ |
| 793 | UINT8 st1 = v&1; |
| 794 | UINT8 st2 = (v>>1)&1; |
| 795 | /* IRQRST,T1MSK,t2MSK,EOSMSK,BRMSK,x,ST2,ST1 */ |
| 796 | OPL_STATUS_RESET(OPL,v&0x78); |
| 797 | OPL_STATUSMASK_SET(OPL,((~v)&0x78)|0x01); |
| 798 | /* timer 2 */ |
| 799 | if(OPL->st[1] != st2) |
| 800 | { |
| 801 | double interval = st2 ? (double)OPL->T[1]*OPL->TimerBase : 0.0; |
| 802 | OPL->st[1] = st2; |
| 803 | if (OPL->TimerHandler) (OPL->TimerHandler)(OPL->TimerParam+1,interval); |
| 804 | } |
| 805 | /* timer 1 */ |
| 806 | if(OPL->st[0] != st1) |
| 807 | { |
| 808 | double interval = st1 ? (double)OPL->T[0]*OPL->TimerBase : 0.0; |
| 809 | OPL->st[0] = st1; |
no test coverage detected