---------- reset one of chip ---------- */
| 1161 | |
| 1162 | /* ---------- reset one of chip ---------- */ |
| 1163 | void OPLResetChip(FM_OPL *OPL) |
| 1164 | { |
| 1165 | int c,s; |
| 1166 | int i; |
| 1167 | |
| 1168 | /* reset chip */ |
| 1169 | OPL->mode = 0; /* normal mode */ |
| 1170 | OPL_STATUS_RESET(OPL,0x7f); |
| 1171 | /* reset with register write */ |
| 1172 | OPLWriteReg(OPL,0x01,0); /* wabesel disable */ |
| 1173 | OPLWriteReg(OPL,0x02,0); /* Timer1 */ |
| 1174 | OPLWriteReg(OPL,0x03,0); /* Timer2 */ |
| 1175 | OPLWriteReg(OPL,0x04,0); /* IRQ mask clear */ |
| 1176 | for(i = 0xff ; i >= 0x20 ; i-- ) OPLWriteReg(OPL,i,0); |
| 1177 | /* reset OPerator parameter */ |
| 1178 | for( c = 0 ; c < OPL->max_ch ; c++ ) |
| 1179 | { |
| 1180 | OPL_CH *CH = &OPL->P_CH[c]; |
| 1181 | /* OPL->P_CH[c].PAN = OPN_CENTER; */ |
| 1182 | for(s = 0 ; s < 2 ; s++ ) |
| 1183 | { |
| 1184 | /* wave table */ |
| 1185 | CH->SLOT[s].wavetable = &SIN_TABLE[0]; |
| 1186 | /* CH->SLOT[s].evm = ENV_MOD_RR; */ |
| 1187 | CH->SLOT[s].evc = EG_OFF; |
| 1188 | CH->SLOT[s].eve = EG_OFF+1; |
| 1189 | CH->SLOT[s].evs = 0; |
| 1190 | } |
| 1191 | } |
| 1192 | #if BUILD_Y8950 |
| 1193 | if(OPL->type&OPL_TYPE_ADPCM) |
| 1194 | { |
| 1195 | YM_DELTAT *DELTAT = OPL->deltat; |
| 1196 | |
| 1197 | DELTAT->freqbase = OPL->freqbase; |
| 1198 | DELTAT->output_pointer = outd; |
| 1199 | DELTAT->portshift = 5; |
| 1200 | DELTAT->output_range = DELTAT_MIXING_LEVEL<<TL_BITS; |
| 1201 | YM_DELTAT_ADPCM_Reset(DELTAT,0); |
| 1202 | } |
| 1203 | #endif |
| 1204 | } |
| 1205 | |
| 1206 | /* ---------- Create one of virtual YM3812 ---------- */ |
| 1207 | /* 'rate' is sampling rate and 'bufsiz' is the size of the */ |
no test coverage detected