Emits a compressed load instruction. These consist of: funct3 | imm | rs1 | imm | rd | op
| 44 | // Emits a compressed load instruction. These consist of: |
| 45 | // funct3 | imm | rs1 | imm | rd | op |
| 46 | void EmitCompressedLoad(CodeBuffer& buffer, uint32_t funct3, uint32_t imm, GPR rs, |
| 47 | Register rd, uint32_t op) { |
| 48 | BISCUIT_ASSERT(IsValid3BitCompressedReg(rs)); |
| 49 | BISCUIT_ASSERT(IsValid3BitCompressedReg(rd)); |
| 50 | |
| 51 | imm &= 0xF8; |
| 52 | |
| 53 | const auto imm_enc = ((imm & 0x38) << 7) | ((imm & 0xC0) >> 1); |
| 54 | const auto rd_san = CompressedRegTo3BitEncoding(rd); |
| 55 | const auto rs_san = CompressedRegTo3BitEncoding(rs); |
| 56 | buffer.Emit16(((funct3 & 0b111) << 13) | imm_enc | (rs_san << 7) | (rd_san << 2) | (op & 0b11)); |
| 57 | } |
| 58 | |
| 59 | // Emits a compressed register arithmetic instruction. These consist of: |
| 60 | // funct6 | rd | funct2 | rs | op |
no test coverage detected