Container of informations about test

* Container of the bitstring or the exact integer value * * @note if bitstring_base == INVALID_BASE the integer value "val" is used * otherwise t

* HDL AST node for for-in-statement * */

* HDL AST node for block statement (begin-end in SV) * */

* HDL AST node for value of arrays * */

Use file to store the filter of the tests and do not execute them again

* Container for position in code. * NOTE: stopXX are inclusive coordinates and not one beyond i.e. [startXXX, stopXXX] and not [startXXX, stopXXX) *

Swaps the file_line_map in logger and on destruction it will put it back.

* Container of any HDL objects * */

* HDL AST node which purpose is used if conversion of original expression is not implemented * */

* HDL AST node for definition or declaration of HDL function/task etc. * */

* HDL AST node for definition of * port, constant, signal, typedef, VHDL generic, Verilog param and localparam * * @note if variable is a port the

* HDL library reference * */

* HDL AST node for module declaration * (part with ports and params for Verilog, Entity for VHDL) * */

* HDL AST node for module definition (the body of the module in Verilog, Architecture in VHDL) * */

* HDL AST node for call of HDL function or operator * */

A base class for HDL parser tests

* HDL AST node for assignment statement * */

* HDL AST node for loop-control statements * */

* HDL AST node for switch-case statement * */

* HDL AST node for do-while-statement * */

* HDL AST node for expression statement, wrapper around expression which adds label, code position etc. * */

* HDL AST node for for-statement * */

* HDL AST node for conditional statement * */

* HDL AST node for nop statement * */

* HDL AST node for HDL process construct * (Verilog always and assign constructs, VHDL process and top level assignments) * * @note the process may

* HDL AST node for repeat-statement * */

* HDL AST node for while-statement * */

* HDL AST node for float/real value * */

* HDL AST node for HDL id * */

* HDL AST node for namespace (namespace in System Verilog, package/package body in VHDL) * */

* HDL AST node for integer/bitstring value * */

* HDL AST node for string value * */

* HDL AST node for special hdl symbols * */

* class MacroDefVerilog is an object to to store a verilog preprocessor macro definition * and to perform it's function * Example: * `define my_s

* Base class for HDL object with name * */

* The comment parser reads the text from the hidden tokens * generated from the antlr lexer. This tokens are not connected * to a AST tree and they

* The class which implements ANTLR error listener which is installed in parser * and lexer and staging the errors for later check. * */

* Parser of other SystemVerilog declarations * */