↓ 4 callersMethodencodeMovzWEncode MOVZ Wd, #imm16 (32-bit). Format: `[31] = 0 (sf)`, `[30:29] = 10`, `[28:23] = 100101`, `[22:21] = hw`, `[20:5] = imm16`, `[4:0] = Rd`
sources/FirmwarePatcher/ARM64/ARM64Encoder.swift:97
↓ 3 callersMethodencodeMovXEncode `MOV Xd, Xm` (the ORR Xd, XZR, Xm alias). With `rm == 31` (XZR) this is the canonical "zero a 64-bit register" (`mov xd, xzr`). Format: `[31]
sources/FirmwarePatcher/ARM64/ARM64Encoder.swift:117