()
| 388 | pmpaddr0: u64::MAX, |
| 389 | }; |
| 390 | |
| 391 | let mut tlb = Tlb::new(); |
| 392 | let fetched = crate::cpu::pipeline::fetch::fetch_with_pmp( |
| 393 | &mut bus, |
| 394 | crate::bus::RAM_BASE, |
| 395 | ctx, |
| 396 | &mut tlb, |
| 397 | ) |
| 398 | .expect("fetch should succeed"); |
| 399 | |
| 400 | assert_eq!(fetched, instr); |
| 401 | } |
| 402 | |
| 403 | #[test] |
| 404 | fn pmp_blocks_execute_when_x_clear() { |
| 405 | let mut bus = SystemBus::new(vec![]); |
| 406 | let instr: u32 = 0x0000_0013; // addi x0,x0,0 |
| 407 | let _ = bus.write_word(crate::bus::RAM_BASE, instr); |
| 408 | |
| 409 | let ctx = TranslationContext { |
| 410 | satp: 0, |
| 411 | priv_mode: crate::cpu::registers::PrivilegeMode::Supervisor, |
| 412 | mstatus: 0, |
| 413 | pmpcfg0: 0x3, |
| 414 | pmpaddr0: u64::MAX, |
| 415 | }; |
| 416 | |
| 417 | let mut tlb = Tlb::new(); |
| 418 | let res = crate::cpu::pipeline::fetch::fetch_with_pmp( |
| 419 | &mut bus, |
| 420 | crate::bus::RAM_BASE, |
| 421 | ctx, |
| 422 | &mut tlb, |
nothing calls this directly
no test coverage detected