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Types & classes80 in github.com/IsaacMarovitz/tetsuyu

⨍ Functions 313◇ Types & classes 80

src/sound/apu.rs:7

src/config.rs:96

src/hw/cpu.rs:30

src/hw/cpu.rs:24

APU as a bus peer. Its frame sequencer is clocked by the timer's DIV, so the motherboard advances it each M-cycle with the current DIV value rather th

src/hw/apu.rs:10

src/components/ppu/bgpi.rs:1

src/mbc/mbc1.rs:90

src/hw/bus.rs:5

src/hw/bus.rs:15

src/hw/cpu.rs:33

src/components/mode.rs:10

src/mbc/header.rs:85

src/sound/ch1.rs:7

src/sound/ch2.rs:7

src/sound/ch3.rs:7

src/sound/ch4.rs:5

src/mbc/mode.rs:6

ClassCh3BlipNode

src/sound/ch3_blip.rs:90

ClassCh3BlipProducer

src/sound/ch3_blip.rs:24

A peer chip on the bus, with its two hardware-distinct interfaces separated: - `advance` steps the chip's internal clock by one dot. `base_dot` gates

src/hw/bus.rs:76

Owns *time* and nothing else. It does not own or step any chip; its only job is to turn CPU T-cycles into base-clock dots, accounting for the double-s

src/hw/clock.rs:5

src/config.rs:73

ClassColorCorrection

Adapted from SameBoy Color Correction

src/components/ppu/cc.rs:17

src/hw/cpu.rs:21

src/config.rs:6

src/context.rs:10

src/hw/cpu.rs:176

EnumDestination

src/mbc/header.rs:79

The DMA engine: OAM DMA (0xFF46) and CGB HDMA/GPDMA (0xFF51-0xFF55). It owns the registers and the transfer state, but the byte movement itself is dri

src/hw/dma.rs:9

src/hw/cpu.rs:127

src/framebuffer.rs:4

ClassFramebufferReader

src/framebuffer.rs:66

ClassFramebufferWriter

src/framebuffer.rs:16

src/components/mode.rs:4

src/sound/synth.rs:96

src/harness.rs:37

src/mbc/header.rs:8

src/config.rs:117

ClassInterruptController

The interrupt controller. Owns IF ($FF0F) and IE ($FFFF) and decodes them itself. Other chips report IRQs via their `Ticked`; the motherboard funnels

src/hw/interrupt.rs:37

src/components/joypad.rs:19

ClassLengthCounter

src/sound/length_counter.rs:1

ClassLfsrNoiseControlled

src/sound/lfsr_noise.rs:4

src/mbc/licensee.rs:4

src/mbc/mode.rs:133

src/mbc/mbc1.rs:4

src/mbc/mbc2.rs:4

src/mbc/mbc3.rs:5

src/mbc/mbc5.rs:4

src/mbc/mode.rs:111

InterfaceMemory

src/components/memory.rs:1

src/hw/cpu.rs:115

ClassMotherboard

The mainboard: owns the chips, the clock, and the traces. Its logic is arbitration, routing, and driving the DMA — it holds no peripheral internals an

src/hw/motherboard.rs:18

ClassNoiseChannel

src/sound/synth.rs:67

src/components/ppu/ppu.rs:14

src/config.rs:37

src/components/ppu/structs.rs:11

src/config.rs:52

ClassPeriodTimer

A down-counting timer shared by the tone and wave channels. It advances one T-cycle per `tick` and, when the period elapses, reloads with the caller's

src/sound/period_timer.rs:7

The shared traces. Exactly one master drives them per M-cycle; every chip watches them and asserts data / latches writes only on the transfer dot.

src/hw/bus.rs:22

The PPU as a peer chip. It owns the existing dot-accurate line renderer and adapts it to the bus. The renderer is boxed: it embeds ~384 KB of color lo

src/hw/ppu.rs:13

src/components/ppu/structs.rs:4

ClassPulseChannel

src/sound/synth.rs:11

src/hw/cpu.rs:15

src/hw/cpu.rs:18

src/hw/cpu.rs:12

src/mbc/rom_only.rs:4

src/mbc/mbc3.rs:79

src/components/registers.rs:7

src/hw/cpu.rs:27

src/harness.rs:30

TODO: Handle serial properly

src/components/serial.rs:6

EnumStopCondition

src/harness.rs:18

src/sound/synth.rs:115

Everything on the bus that is passive memory or an untimed port: the cartridge (MBC) with the boot-rom overlay, work RAM, high RAM, the serial and joy

src/hw/sysbus.rs:16

src/hw/bus.rs:53

DIV/TIMA timer as a peer chip. The internal 16-bit counter advances one step per dot (CPU-clock domain). DIV is the high byte; TIMA is clocked on the

src/hw/timer.rs:8

ClassVolumeEnvelope

src/sound/volume_envelope.rs:1

ClassWaveChannel

src/sound/synth.rs:40