| 503 | } |
| 504 | |
| 505 | void |
| 506 | platform_start(__register_t a0 __unused, |
| 507 | __register_t a1 __unused, |
| 508 | __register_t a2 __unused, |
| 509 | __register_t a3 __unused) |
| 510 | { |
| 511 | |
| 512 | /* Initialize pcpu stuff */ |
| 513 | mips_pcpu0_init(); |
| 514 | |
| 515 | /* initialize console so that we have printf */ |
| 516 | boothowto |= (RB_SERIAL | RB_MULTIPLE); /* Use multiple consoles */ |
| 517 | |
| 518 | init_static_kenv(boot1_env, sizeof(boot1_env)); |
| 519 | xlp_bootargs_init(a0); |
| 520 | |
| 521 | /* clockrate used by delay, so initialize it here */ |
| 522 | xlp_cpu_frequency = xlp_get_cpu_frequency(0, 0); |
| 523 | cpu_clock = xlp_cpu_frequency / 1000000; |
| 524 | mips_timer_early_init(xlp_cpu_frequency); |
| 525 | |
| 526 | /* Init console please */ |
| 527 | cninit(); |
| 528 | |
| 529 | /* Early core init and fixes for errata */ |
| 530 | xlp_setup_core(); |
| 531 | |
| 532 | xlp_parse_mmu_options(); |
| 533 | xlp_mem_init(); |
| 534 | |
| 535 | bcopy(XLPResetEntry, (void *)MIPS_RESET_EXC_VEC, |
| 536 | XLPResetEntryEnd - XLPResetEntry); |
| 537 | #ifdef SMP |
| 538 | /* |
| 539 | * We will enable the other threads in core 0 here |
| 540 | * so that the TLB and cache info is correct when |
| 541 | * mips_init runs |
| 542 | */ |
| 543 | xlp_enable_threads(xlp_mmuval); |
| 544 | #endif |
| 545 | /* setup for the startup core */ |
| 546 | xlp_setup_mmu(); |
| 547 | |
| 548 | xlp_enable_blocks(); |
| 549 | |
| 550 | /* Read/Guess/setup board information */ |
| 551 | nlm_board_info_setup(); |
| 552 | |
| 553 | /* MIPS generic init */ |
| 554 | mips_init(); |
| 555 | |
| 556 | /* |
| 557 | * XLP specific post initialization |
| 558 | * initialize other on chip stuff |
| 559 | */ |
| 560 | xlp_pic_init(); |
| 561 | |
| 562 | mips_timer_init_params(xlp_cpu_frequency, 0); |
nothing calls this directly
no test coverage detected