| 627 | } |
| 628 | |
| 629 | void |
| 630 | platform_init_ap(int cpuid) |
| 631 | { |
| 632 | uint32_t stat; |
| 633 | int thr; |
| 634 | |
| 635 | /* The first thread has to setup the MMU and enable other threads */ |
| 636 | thr = nlm_threadid(); |
| 637 | if (thr == 0) { |
| 638 | xlp_setup_core(); |
| 639 | xlp_enable_threads(xlp_mmuval); |
| 640 | } else { |
| 641 | /* |
| 642 | * FIXME busy wait here eats too many cycles, especially |
| 643 | * in the core 0 while bootup |
| 644 | */ |
| 645 | while (thr_unblock[thr] == 0) |
| 646 | __asm__ __volatile__ ("nop;nop;nop;nop"); |
| 647 | thr_unblock[thr] = 0; |
| 648 | } |
| 649 | |
| 650 | xlp_setup_mmu(); |
| 651 | stat = mips_rd_status(); |
| 652 | KASSERT((stat & MIPS_SR_INT_IE) == 0, |
| 653 | ("Interrupts enabled in %s!", __func__)); |
| 654 | stat |= MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT; |
| 655 | mips_wr_status(stat); |
| 656 | |
| 657 | nlm_write_c0_eimr(0ull); |
| 658 | xlp_enable_irq(IRQ_IPI); |
| 659 | xlp_enable_irq(IRQ_TIMER); |
| 660 | xlp_enable_irq(IRQ_MSGRING); |
| 661 | |
| 662 | return; |
| 663 | } |
| 664 | |
| 665 | int |
| 666 | platform_ipi_hardintr_num(void) |
nothing calls this directly
no test coverage detected