* Initialize special VIA features */
| 563 | * Initialize special VIA features |
| 564 | */ |
| 565 | static void |
| 566 | init_via(void) |
| 567 | { |
| 568 | u_int regs[4], val; |
| 569 | uint64_t fcr; |
| 570 | |
| 571 | /* |
| 572 | * Explicitly enable CX8 and PGE on C3. |
| 573 | * |
| 574 | * http://www.via.com.tw/download/mainboards/6/13/VIA_C3_EBGA%20datasheet110.pdf |
| 575 | */ |
| 576 | if (CPUID_TO_MODEL(cpu_id) <= 9) |
| 577 | fcr = (1 << 1) | (1 << 7); |
| 578 | else |
| 579 | fcr = 0; |
| 580 | |
| 581 | /* |
| 582 | * Check extended CPUID for PadLock features. |
| 583 | * |
| 584 | * http://www.via.com.tw/en/downloads/whitepapers/initiatives/padlock/programming_guide.pdf |
| 585 | */ |
| 586 | do_cpuid(0xc0000000, regs); |
| 587 | if (regs[0] >= 0xc0000001) { |
| 588 | do_cpuid(0xc0000001, regs); |
| 589 | val = regs[3]; |
| 590 | } else |
| 591 | val = 0; |
| 592 | |
| 593 | /* Enable RNG if present. */ |
| 594 | if ((val & VIA_CPUID_HAS_RNG) != 0) { |
| 595 | via_feature_rng = VIA_HAS_RNG; |
| 596 | wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG); |
| 597 | } |
| 598 | |
| 599 | /* Enable PadLock if present. */ |
| 600 | if ((val & VIA_CPUID_HAS_ACE) != 0) |
| 601 | via_feature_xcrypt |= VIA_HAS_AES; |
| 602 | if ((val & VIA_CPUID_HAS_ACE2) != 0) |
| 603 | via_feature_xcrypt |= VIA_HAS_AESCTR; |
| 604 | if ((val & VIA_CPUID_HAS_PHE) != 0) |
| 605 | via_feature_xcrypt |= VIA_HAS_SHA; |
| 606 | if ((val & VIA_CPUID_HAS_PMM) != 0) |
| 607 | via_feature_xcrypt |= VIA_HAS_MM; |
| 608 | if (via_feature_xcrypt != 0) |
| 609 | fcr |= 1 << 28; |
| 610 | |
| 611 | wrmsr(0x1107, rdmsr(0x1107) | fcr); |
| 612 | } |
| 613 | |
| 614 | #endif /* I686_CPU */ |
| 615 |
no test coverage detected