* Initialize BBL_CR_CTL3 (Control register 3: used to configure the * L2 cache). */
| 525 | * L2 cache). |
| 526 | */ |
| 527 | static void |
| 528 | init_mendocino(void) |
| 529 | { |
| 530 | #ifdef CPU_PPRO2CELERON |
| 531 | register_t saveintr; |
| 532 | u_int64_t bbl_cr_ctl3; |
| 533 | |
| 534 | saveintr = intr_disable(); |
| 535 | |
| 536 | load_cr0(rcr0() | CR0_CD | CR0_NW); |
| 537 | wbinvd(); |
| 538 | |
| 539 | bbl_cr_ctl3 = rdmsr(MSR_BBL_CR_CTL3); |
| 540 | |
| 541 | /* If the L2 cache is configured, do nothing. */ |
| 542 | if (!(bbl_cr_ctl3 & 1)) { |
| 543 | bbl_cr_ctl3 = 0x134052bLL; |
| 544 | |
| 545 | /* Set L2 Cache Latency (Default: 5). */ |
| 546 | #ifdef CPU_CELERON_L2_LATENCY |
| 547 | #if CPU_L2_LATENCY > 15 |
| 548 | #error invalid CPU_L2_LATENCY. |
| 549 | #endif |
| 550 | bbl_cr_ctl3 |= CPU_L2_LATENCY << 1; |
| 551 | #else |
| 552 | bbl_cr_ctl3 |= 5 << 1; |
| 553 | #endif |
| 554 | wrmsr(MSR_BBL_CR_CTL3, bbl_cr_ctl3); |
| 555 | } |
| 556 | |
| 557 | load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); |
| 558 | intr_restore(saveintr); |
| 559 | #endif /* CPU_PPRO2CELERON */ |
| 560 | } |
| 561 | |
| 562 | /* |
| 563 | * Initialize special VIA features |
no test coverage detected