| 631 | } |
| 632 | |
| 633 | static void |
| 634 | process_msg(struct tegra_xhci_softc *sc, uint32_t req_cmd, uint32_t req_data, |
| 635 | uint32_t *resp_cmd, uint32_t *resp_data) |
| 636 | { |
| 637 | uint64_t freq; |
| 638 | int rv; |
| 639 | |
| 640 | /* In most cases, data are echoed back. */ |
| 641 | *resp_data = req_data; |
| 642 | switch (req_cmd) { |
| 643 | case MBOX_CMD_INC_FALC_CLOCK: |
| 644 | case MBOX_CMD_DEC_FALC_CLOCK: |
| 645 | rv = clk_set_freq(sc->clk_xusb_falcon_src, req_data * 1000ULL, |
| 646 | 0); |
| 647 | if (rv == 0) { |
| 648 | rv = clk_get_freq(sc->clk_xusb_falcon_src, &freq); |
| 649 | *resp_data = (uint32_t)(freq / 1000); |
| 650 | } |
| 651 | *resp_cmd = rv == 0 ? MBOX_CMD_ACK: MBOX_CMD_NAK; |
| 652 | break; |
| 653 | |
| 654 | case MBOX_CMD_INC_SSPI_CLOCK: |
| 655 | case MBOX_CMD_DEC_SSPI_CLOCK: |
| 656 | rv = clk_set_freq(sc->clk_xusb_ss, req_data * 1000ULL, |
| 657 | 0); |
| 658 | if (rv == 0) { |
| 659 | rv = clk_get_freq(sc->clk_xusb_ss, &freq); |
| 660 | *resp_data = (uint32_t)(freq / 1000); |
| 661 | } |
| 662 | *resp_cmd = rv == 0 ? MBOX_CMD_ACK: MBOX_CMD_NAK; |
| 663 | break; |
| 664 | |
| 665 | case MBOX_CMD_SET_BW: |
| 666 | /* No respense is expected. */ |
| 667 | *resp_cmd = 0; |
| 668 | break; |
| 669 | |
| 670 | case MBOX_CMD_SET_SS_PWR_GATING: |
| 671 | case MBOX_CMD_SET_SS_PWR_UNGATING: |
| 672 | *resp_cmd = MBOX_CMD_NAK; |
| 673 | break; |
| 674 | |
| 675 | case MBOX_CMD_SAVE_DFE_CTLE_CTX: |
| 676 | /* Not implemented yet. */ |
| 677 | *resp_cmd = MBOX_CMD_ACK; |
| 678 | break; |
| 679 | |
| 680 | case MBOX_CMD_START_HSIC_IDLE: |
| 681 | case MBOX_CMD_STOP_HSIC_IDLE: |
| 682 | /* Not implemented yet. */ |
| 683 | *resp_cmd = MBOX_CMD_NAK; |
| 684 | break; |
| 685 | |
| 686 | case MBOX_CMD_DISABLE_SS_LFPS_DETECTION: |
| 687 | case MBOX_CMD_ENABLE_SS_LFPS_DETECTION: |
| 688 | /* Not implemented yet. */ |
| 689 | *resp_cmd = MBOX_CMD_NAK; |
| 690 | break; |
no test coverage detected