| 706 | } |
| 707 | |
| 708 | static void |
| 709 | intr_mbox(void *arg) |
| 710 | { |
| 711 | struct tegra_xhci_softc *sc; |
| 712 | uint32_t reg, msg, resp_cmd, resp_data; |
| 713 | |
| 714 | sc = (struct tegra_xhci_softc *)arg; |
| 715 | |
| 716 | /* Clear interrupt first */ |
| 717 | reg = FPCI_RD4(sc, XUSB_CFG_ARU_SMI_INTR); |
| 718 | FPCI_WR4(sc, XUSB_CFG_ARU_SMI_INTR, reg); |
| 719 | if (reg & ARU_SMI_INTR_FW_HANG) { |
| 720 | device_printf(sc->dev, |
| 721 | "XUSB CPU firmware hang!!! CPUCTL: 0x%08X\n", |
| 722 | CSB_RD4(sc, XUSB_FALCON_CPUCTL)); |
| 723 | } |
| 724 | |
| 725 | msg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_DATA_OUT); |
| 726 | resp_cmd = 0; |
| 727 | process_msg(sc, ARU_MAILBOX_DATA_OUT_TYPE(msg), |
| 728 | ARU_MAILBOX_DATA_OUT_DATA(msg), &resp_cmd, &resp_data); |
| 729 | if (resp_cmd != 0) |
| 730 | mbox_send_ack(sc, resp_cmd, resp_data); |
| 731 | else |
| 732 | FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_OWNER, |
| 733 | ARU_MAILBOX_OWNER_NONE); |
| 734 | |
| 735 | reg = FPCI_RD4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD); |
| 736 | reg &= ~ARU_MAILBOX_CMD_DEST_SMI; |
| 737 | FPCI_WR4(sc, T_XUSB_CFG_ARU_MAILBOX_CMD, reg); |
| 738 | |
| 739 | } |
| 740 | |
| 741 | static int |
| 742 | load_fw(struct tegra_xhci_softc *sc) |
nothing calls this directly
no test coverage detected