------------------------------------------------------------------- * * Bus and infrastructure. * */
| 1096 | * |
| 1097 | */ |
| 1098 | static int |
| 1099 | dc_init_planes(struct dc_softc *sc, struct tegra_drm *drm) |
| 1100 | { |
| 1101 | int i, rv; |
| 1102 | struct tegra_plane *plane; |
| 1103 | |
| 1104 | rv = 0; |
| 1105 | for (i = 0; i < DC_MAX_PLANES; i++) { |
| 1106 | plane = malloc(sizeof(*plane), DRM_MEM_KMS, M_WAITOK | M_ZERO); |
| 1107 | plane->index = i + 1; |
| 1108 | rv = drm_plane_init(&drm->drm_dev, &plane->drm_plane, |
| 1109 | 1 << sc->tegra_crtc.nvidia_head, &dc_plane_funcs, |
| 1110 | dc_plane_formats, nitems(dc_plane_formats), false); |
| 1111 | if (rv != 0) { |
| 1112 | free(plane, DRM_MEM_KMS); |
| 1113 | return (rv); |
| 1114 | } |
| 1115 | } |
| 1116 | return 0; |
| 1117 | } |
| 1118 | |
| 1119 | static void |
| 1120 | dc_display_enable(device_t dev, bool enable) |
no test coverage detected