Function dc_init_client

freebsd/arm/nvidia/drm2/tegra_dc.c:1191–1236

}

static int
dc_init_client(device_t dev, device_t host1x, struct tegra_drm *drm)
{
	struct dc_softc *sc;
	int rv;

	sc = device_get_softc(dev);

	if (drm->pitch_align < sc->pitch_align)
		drm->pitch_align = sc->pitch_align;

	drm_crtc_init(&drm->drm_dev, &sc->tegra_crtc.drm_crtc, &dc_crtc_funcs);
	drm_mode_crtc_set_gamma_size(&sc->tegra_crtc.drm_crtc, 256);
	drm_crtc_helper_add(&sc->tegra_crtc.drm_crtc, &dc_crtc_helper_funcs);

	rv = dc_init_planes(sc, drm);
	if (rv!= 0){
		device_printf(dev, "Cannot init planes\n");
		return (rv);
	}

	WR4(sc, DC_CMD_INT_TYPE,
	    WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
	    WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT);

	WR4(sc, DC_CMD_INT_POLARITY,
	    WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
	    WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT);

	WR4(sc, DC_CMD_INT_ENABLE, 0);
	WR4(sc, DC_CMD_INT_MASK, 0);

	rv = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
	    NULL, dc_intr, sc, &sc->irq_ih);
	if (rv != 0) {
		device_printf(dev, "Cannot register interrupt handler\n");
		return (rv);
	}

	/* allocate memory for cursor cache */
	sc->tegra_crtc.cursor_vbase = kmem_alloc_contig(256 * 256 * 4,
	    M_WAITOK | M_ZERO, 0, -1UL, PAGE_SIZE, 0,
	    VM_MEMATTR_WRITE_COMBINING);
	sc->tegra_crtc.cursor_pbase = vtophys(sc->tegra_crtc.cursor_vbase);
	return (0);
}

static int
dc_exit_client(device_t dev, device_t host1x, struct tegra_drm *drm)