Sync I and D caches to PoU */
| 456 | |
| 457 | /* Sync I and D caches to PoU */ |
| 458 | static __inline void |
| 459 | icache_sync(vm_offset_t va, vm_size_t size) |
| 460 | { |
| 461 | vm_offset_t eva = va + size; |
| 462 | |
| 463 | dsb(); |
| 464 | va &= ~cpuinfo.dcache_line_mask; |
| 465 | |
| 466 | for ( ; va < eva; va += cpuinfo.dcache_line_size) { |
| 467 | #if __ARM_ARCH >= 7 |
| 468 | _CP15_DCCMVAU(va); |
| 469 | #else |
| 470 | _CP15_DCCMVAC(va); |
| 471 | #endif |
| 472 | } |
| 473 | dsb(); |
| 474 | ARM_SMP_UP( |
| 475 | _CP15_ICIALLUIS(), |
| 476 | _CP15_ICIALLU() |
| 477 | ); |
| 478 | dsb(); |
| 479 | isb(); |
| 480 | } |
| 481 | |
| 482 | /* Invalidate I cache */ |
| 483 | static __inline void |
no outgoing calls
no test coverage detected