* Write bytes to kernel address space for debugger. */
| 216 | * Write bytes to kernel address space for debugger. |
| 217 | */ |
| 218 | int |
| 219 | db_write_bytes(vm_offset_t addr, size_t size, char *data) |
| 220 | { |
| 221 | char *dst; |
| 222 | size_t loop; |
| 223 | |
| 224 | dst = (char *)addr; |
| 225 | if (db_validate_address((u_int)dst)) { |
| 226 | db_printf("address %p is invalid\n", dst); |
| 227 | return (0); |
| 228 | } |
| 229 | |
| 230 | if (size == 4 && (addr & 3) == 0 && ((uintptr_t)data & 3) == 0) |
| 231 | *((int*)dst) = *((int*)data); |
| 232 | else |
| 233 | if (size == 2 && (addr & 1) == 0 && ((uintptr_t)data & 1) == 0) |
| 234 | *((short*)dst) = *((short*)data); |
| 235 | else { |
| 236 | loop = size; |
| 237 | while (loop-- > 0) { |
| 238 | if (db_validate_address((u_int)dst)) { |
| 239 | db_printf("address %p is invalid\n", dst); |
| 240 | return (-1); |
| 241 | } |
| 242 | *dst++ = *data++; |
| 243 | } |
| 244 | } |
| 245 | |
| 246 | /* make sure the caches and memory are in sync */ |
| 247 | icache_sync(addr, size); |
| 248 | |
| 249 | /* In case the current page tables have been modified ... */ |
| 250 | tlb_flush_all(); |
| 251 | return (0); |
| 252 | } |
| 253 | |
| 254 | static u_int |
| 255 | db_fetch_reg(int reg) |
no test coverage detected