| 975 | CTASSERT(sizeof(struct dbreg) == sizeof(((struct pcpu *)NULL)->pc_dbreg)); |
| 976 | |
| 977 | void |
| 978 | dbg_monitor_init_secondary(void) |
| 979 | { |
| 980 | u_int cpuid; |
| 981 | int err; |
| 982 | /* |
| 983 | * This flag is set on the primary CPU |
| 984 | * and its meaning is valid for other CPUs too. |
| 985 | */ |
| 986 | if (!dbg_capable()) |
| 987 | return; |
| 988 | |
| 989 | cpuid = PCPU_GET(cpuid); |
| 990 | |
| 991 | err = dbg_reset_state(); |
| 992 | if (err != 0) { |
| 993 | /* |
| 994 | * Something is very wrong. |
| 995 | * WPs/BPs will not work correctly on this CPU. |
| 996 | */ |
| 997 | KASSERT(0, ("%s: Failed to reset Debug Architecture " |
| 998 | "state on CPU%d", __func__, cpuid)); |
| 999 | /* Disable HW debug capabilities for all CPUs */ |
| 1000 | atomic_set_int(&dbg_capable_var, 0); |
| 1001 | return; |
| 1002 | } |
| 1003 | err = dbg_enable_monitor(); |
| 1004 | if (err != 0) { |
| 1005 | KASSERT(0, ("%s: Failed to enable Debug Monitor" |
| 1006 | " on CPU%d", __func__, cpuid)); |
| 1007 | atomic_set_int(&dbg_capable_var, 0); |
| 1008 | } |
| 1009 | } |
| 1010 | |
| 1011 | void |
| 1012 | dbg_resume_dbreg(void) |
no test coverage detected