| 927 | } |
| 928 | |
| 929 | void |
| 930 | dbg_monitor_init(void) |
| 931 | { |
| 932 | int err; |
| 933 | |
| 934 | /* Fetch ARM Debug Architecture model */ |
| 935 | dbg_model = dbg_get_debug_model(); |
| 936 | |
| 937 | if (!dbg_arch_supported()) { |
| 938 | db_printf("ARM Debug Architecture not supported\n"); |
| 939 | return; |
| 940 | } |
| 941 | |
| 942 | if (bootverbose) { |
| 943 | db_printf("ARM Debug Architecture %s\n", |
| 944 | (dbg_model == ID_DFR0_CP_DEBUG_M_V6) ? "v6" : |
| 945 | (dbg_model == ID_DFR0_CP_DEBUG_M_V6_1) ? "v6.1" : |
| 946 | (dbg_model == ID_DFR0_CP_DEBUG_M_V7) ? "v7" : |
| 947 | (dbg_model == ID_DFR0_CP_DEBUG_M_V7_1) ? "v7.1" : "unknown"); |
| 948 | } |
| 949 | |
| 950 | /* Do we have OS Save and Restore mechanism? */ |
| 951 | dbg_ossr = dbg_get_ossr(); |
| 952 | |
| 953 | /* Find out many breakpoints and watchpoints we can use */ |
| 954 | dbg_watchpoint_num = dbg_get_wrp_num(); |
| 955 | dbg_breakpoint_num = dgb_get_brp_num(); |
| 956 | |
| 957 | if (bootverbose) { |
| 958 | db_printf("%d watchpoints and %d breakpoints supported\n", |
| 959 | dbg_watchpoint_num, dbg_breakpoint_num); |
| 960 | } |
| 961 | |
| 962 | err = dbg_reset_state(); |
| 963 | if (err == 0) { |
| 964 | err = dbg_enable_monitor(); |
| 965 | if (err == 0) { |
| 966 | atomic_set_int(&dbg_capable_var, 1); |
| 967 | return; |
| 968 | } |
| 969 | } |
| 970 | |
| 971 | db_printf("HW Breakpoints/Watchpoints not enabled on CPU%d\n", |
| 972 | PCPU_GET(cpuid)); |
| 973 | } |
| 974 | |
| 975 | CTASSERT(sizeof(struct dbreg) == sizeof(((struct pcpu *)NULL)->pc_dbreg)); |
| 976 |
no test coverage detected