| 188 | } |
| 189 | |
| 190 | static void |
| 191 | pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes) |
| 192 | { |
| 193 | int port; |
| 194 | |
| 195 | mtx_lock_spin(&pcicfg_mtx); |
| 196 | port = pci_cfgenable(bus, slot, func, reg, bytes); |
| 197 | if (port != 0) { |
| 198 | switch (bytes) { |
| 199 | case 1: |
| 200 | outb(port, data); |
| 201 | break; |
| 202 | case 2: |
| 203 | outw(port, data); |
| 204 | break; |
| 205 | case 4: |
| 206 | outl(port, data); |
| 207 | break; |
| 208 | } |
| 209 | pci_cfgdisable(); |
| 210 | } |
| 211 | mtx_unlock_spin(&pcicfg_mtx); |
| 212 | } |
| 213 | |
| 214 | int |
| 215 | pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus) |
no test coverage detected