* Write configuration space register */
| 119 | * Write configuration space register |
| 120 | */ |
| 121 | void |
| 122 | pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes) |
| 123 | { |
| 124 | |
| 125 | if (cfgmech == CFGMECH_PCIE && |
| 126 | (bus >= pcie_minbus && bus <= pcie_maxbus) && |
| 127 | (bus != 0 || !(1 << slot & pcie_badslots))) |
| 128 | pciereg_cfgwrite(bus, slot, func, reg, data, bytes); |
| 129 | else |
| 130 | pcireg_cfgwrite(bus, slot, func, reg, data, bytes); |
| 131 | } |
| 132 | |
| 133 | /* |
| 134 | * Configuration space access using direct register operations |
nothing calls this directly
no test coverage detected