* set the IVAR registers, mapping interrupt causes to vectors * @param hw * pointer to txgbe_hw struct * @direction * 0 for Rx, 1 for Tx, -1 for other causes * @queue * queue to map the corresponding interrupt to * @msix_vector * the vector to map to the corresponding queue */
| 3901 | * the vector to map to the corresponding queue |
| 3902 | */ |
| 3903 | void |
| 3904 | txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction, |
| 3905 | uint8_t queue, uint8_t msix_vector) |
| 3906 | { |
| 3907 | uint32_t tmp, idx; |
| 3908 | |
| 3909 | if (direction == -1) { |
| 3910 | /* other causes */ |
| 3911 | msix_vector |= TXGBE_IVARMISC_VLD; |
| 3912 | idx = 0; |
| 3913 | tmp = rd32(hw, TXGBE_IVARMISC); |
| 3914 | tmp &= ~(0xFF << idx); |
| 3915 | tmp |= (msix_vector << idx); |
| 3916 | wr32(hw, TXGBE_IVARMISC, tmp); |
| 3917 | } else { |
| 3918 | /* rx or tx causes */ |
| 3919 | msix_vector |= TXGBE_IVAR_VLD; /* Workaround for ICR lost */ |
| 3920 | idx = ((16 * (queue & 1)) + (8 * direction)); |
| 3921 | tmp = rd32(hw, TXGBE_IVAR(queue >> 1)); |
| 3922 | tmp &= ~(0xFF << idx); |
| 3923 | tmp |= (msix_vector << idx); |
| 3924 | wr32(hw, TXGBE_IVAR(queue >> 1), tmp); |
| 3925 | } |
| 3926 | } |
| 3927 | |
| 3928 | /** |
| 3929 | * Sets up the hardware to properly generate MSI-X interrupts |
no test coverage detected