Function mlx5_txpp_create_clock_queue

dpdk/drivers/net/mlx5/mlx5_txpp.c:384–471

Creates the Clock Queue for packet pacing, returns zero on success. */

/* Creates the Clock Queue for packet pacing, returns zero on success. */
static int
mlx5_txpp_create_clock_queue(struct mlx5_dev_ctx_shared *sh)
{
	struct mlx5_devx_create_sq_attr sq_attr = { 0 };
	struct mlx5_devx_modify_sq_attr msq_attr = { 0 };
	struct mlx5_devx_cq_attr cq_attr = {
		.use_first_only = 1,
		.overrun_ignore = 1,
		.uar_page_id = mlx5_os_get_devx_uar_page_id(sh->tx_uar.obj),
	};
	struct mlx5_txpp_wq *wq = &sh->txpp.clock_queue;
	int ret;

	sh->txpp.tsa = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,
				   MLX5_TXPP_REARM_SQ_SIZE *
				   sizeof(struct mlx5_txpp_ts),
				   0, sh->numa_node);
	if (!sh->txpp.tsa) {
		DRV_LOG(ERR, "Failed to allocate memory for CQ stats.");
		return -ENOMEM;
	}
	sh->txpp.ts_p = 0;
	sh->txpp.ts_n = 0;
	/* Create completion queue object for Clock Queue. */
	ret = mlx5_devx_cq_create(sh->cdev->ctx, &wq->cq_obj,
				  log2above(MLX5_TXPP_CLKQ_SIZE), &cq_attr,
				  sh->numa_node);
	if (ret) {
		DRV_LOG(ERR, "Failed to create CQ for Clock Queue.");
		goto error;
	}
	wq->cq_ci = 0;
	/* Allocate memory buffer for Send Queue WQEs. */
	if (sh->txpp.test) {
		wq->sq_size = RTE_ALIGN(MLX5_TXPP_TEST_PKT_SIZE +
					MLX5_WQE_CSEG_SIZE +
					2 * MLX5_WQE_ESEG_SIZE -
					MLX5_ESEG_MIN_INLINE_SIZE,
					MLX5_WQE_SIZE) / MLX5_WQE_SIZE;
		wq->sq_size *= MLX5_TXPP_CLKQ_SIZE;
	} else {
		wq->sq_size = MLX5_TXPP_CLKQ_SIZE;
	}
	/* There should not be WQE leftovers in the cyclic queue. */
	MLX5_ASSERT(wq->sq_size == (1 << log2above(wq->sq_size)));
	/* Create send queue object for Clock Queue. */
	if (sh->txpp.test) {
		sq_attr.tis_lst_sz = 1;
		sq_attr.tis_num = sh->tis[0]->id;
		sq_attr.non_wire = 0;
		sq_attr.static_sq_wq = 1;
	} else {
		sq_attr.non_wire = 1;
		sq_attr.static_sq_wq = 1;
	}
	sq_attr.cqn = wq->cq_obj.cq->id;
	sq_attr.packet_pacing_rate_limit_index = sh->txpp.pp_id;
	sq_attr.wq_attr.cd_slave = 1;