* Initializes Transmit Unit. */
| 5281 | * Initializes Transmit Unit. |
| 5282 | */ |
| 5283 | void __rte_cold |
| 5284 | ixgbe_dev_tx_init(struct rte_eth_dev *dev) |
| 5285 | { |
| 5286 | struct ixgbe_hw *hw; |
| 5287 | struct ixgbe_tx_queue *txq; |
| 5288 | uint64_t bus_addr; |
| 5289 | uint32_t hlreg0; |
| 5290 | uint32_t txctrl; |
| 5291 | uint16_t i; |
| 5292 | |
| 5293 | PMD_INIT_FUNC_TRACE(); |
| 5294 | hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); |
| 5295 | |
| 5296 | /* Enable TX CRC (checksum offload requirement) and hw padding |
| 5297 | * (TSO requirement) |
| 5298 | */ |
| 5299 | hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); |
| 5300 | hlreg0 |= (IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_TXPADEN); |
| 5301 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); |
| 5302 | |
| 5303 | /* Setup the Base and Length of the Tx Descriptor Rings */ |
| 5304 | for (i = 0; i < dev->data->nb_tx_queues; i++) { |
| 5305 | txq = dev->data->tx_queues[i]; |
| 5306 | |
| 5307 | bus_addr = txq->tx_ring_phys_addr; |
| 5308 | IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx), |
| 5309 | (uint32_t)(bus_addr & 0x00000000ffffffffULL)); |
| 5310 | IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx), |
| 5311 | (uint32_t)(bus_addr >> 32)); |
| 5312 | IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx), |
| 5313 | txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc)); |
| 5314 | /* Setup the HW Tx Head and TX Tail descriptor pointers */ |
| 5315 | IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0); |
| 5316 | IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0); |
| 5317 | |
| 5318 | /* |
| 5319 | * Disable Tx Head Writeback RO bit, since this hoses |
| 5320 | * bookkeeping if things aren't delivered in order. |
| 5321 | */ |
| 5322 | switch (hw->mac.type) { |
| 5323 | case ixgbe_mac_82598EB: |
| 5324 | txctrl = IXGBE_READ_REG(hw, |
| 5325 | IXGBE_DCA_TXCTRL(txq->reg_idx)); |
| 5326 | txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; |
| 5327 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx), |
| 5328 | txctrl); |
| 5329 | break; |
| 5330 | |
| 5331 | case ixgbe_mac_82599EB: |
| 5332 | case ixgbe_mac_X540: |
| 5333 | case ixgbe_mac_X550: |
| 5334 | case ixgbe_mac_X550EM_x: |
| 5335 | case ixgbe_mac_X550EM_a: |
| 5336 | default: |
| 5337 | txctrl = IXGBE_READ_REG(hw, |
| 5338 | IXGBE_DCA_TXCTRL_82599(txq->reg_idx)); |
| 5339 | txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; |
| 5340 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx), |
no test coverage detected