| 4706 | } |
| 4707 | |
| 4708 | static int |
| 4709 | ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev) |
| 4710 | { |
| 4711 | struct ixgbe_hw *hw = |
| 4712 | IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); |
| 4713 | uint32_t mtqc; |
| 4714 | uint32_t rttdcs; |
| 4715 | |
| 4716 | if (hw->mac.type == ixgbe_mac_82598EB) |
| 4717 | return 0; |
| 4718 | |
| 4719 | /* disable arbiter before setting MTQC */ |
| 4720 | rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); |
| 4721 | rttdcs |= IXGBE_RTTDCS_ARBDIS; |
| 4722 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); |
| 4723 | |
| 4724 | if (RTE_ETH_DEV_SRIOV(dev).active == 0) { |
| 4725 | /* |
| 4726 | * SRIOV inactive scheme |
| 4727 | * any DCB w/o VMDq multi-queue setting |
| 4728 | */ |
| 4729 | if (dev->data->dev_conf.txmode.mq_mode == RTE_ETH_MQ_TX_VMDQ_ONLY) |
| 4730 | ixgbe_vmdq_tx_hw_configure(hw); |
| 4731 | else { |
| 4732 | mtqc = IXGBE_MTQC_64Q_1PB; |
| 4733 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); |
| 4734 | } |
| 4735 | } else { |
| 4736 | switch (RTE_ETH_DEV_SRIOV(dev).active) { |
| 4737 | |
| 4738 | /* |
| 4739 | * SRIOV active scheme |
| 4740 | * FIXME if support DCB together with VMDq & SRIOV |
| 4741 | */ |
| 4742 | case RTE_ETH_64_POOLS: |
| 4743 | mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF; |
| 4744 | break; |
| 4745 | case RTE_ETH_32_POOLS: |
| 4746 | mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF; |
| 4747 | break; |
| 4748 | case RTE_ETH_16_POOLS: |
| 4749 | mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA | |
| 4750 | IXGBE_MTQC_8TC_8TQ; |
| 4751 | break; |
| 4752 | default: |
| 4753 | mtqc = IXGBE_MTQC_64Q_1PB; |
| 4754 | PMD_INIT_LOG(ERR, "invalid pool number in IOV mode"); |
| 4755 | } |
| 4756 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); |
| 4757 | } |
| 4758 | |
| 4759 | /* re-enable arbiter */ |
| 4760 | rttdcs &= ~IXGBE_RTTDCS_ARBDIS; |
| 4761 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); |
| 4762 | |
| 4763 | return 0; |
| 4764 | } |
| 4765 |
no test coverage detected