| 4581 | } |
| 4582 | |
| 4583 | static int |
| 4584 | ixgbe_config_vf_rss(struct rte_eth_dev *dev) |
| 4585 | { |
| 4586 | struct ixgbe_hw *hw; |
| 4587 | uint32_t mrqc; |
| 4588 | |
| 4589 | ixgbe_rss_configure(dev); |
| 4590 | |
| 4591 | hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); |
| 4592 | |
| 4593 | /* MRQC: enable VF RSS */ |
| 4594 | mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC); |
| 4595 | mrqc &= ~IXGBE_MRQC_MRQE_MASK; |
| 4596 | switch (RTE_ETH_DEV_SRIOV(dev).active) { |
| 4597 | case RTE_ETH_64_POOLS: |
| 4598 | mrqc |= IXGBE_MRQC_VMDQRSS64EN; |
| 4599 | break; |
| 4600 | |
| 4601 | case RTE_ETH_32_POOLS: |
| 4602 | mrqc |= IXGBE_MRQC_VMDQRSS32EN; |
| 4603 | break; |
| 4604 | |
| 4605 | default: |
| 4606 | PMD_INIT_LOG(ERR, "Invalid pool number in IOV mode with VMDQ RSS"); |
| 4607 | return -EINVAL; |
| 4608 | } |
| 4609 | |
| 4610 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); |
| 4611 | |
| 4612 | return 0; |
| 4613 | } |
| 4614 | |
| 4615 | static int |
| 4616 | ixgbe_config_vf_default(struct rte_eth_dev *dev) |
no test coverage detected