| 6120 | } |
| 6121 | |
| 6122 | static void |
| 6123 | ixgbevf_configure_msix(struct rte_eth_dev *dev) |
| 6124 | { |
| 6125 | struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); |
| 6126 | struct rte_intr_handle *intr_handle = pci_dev->intr_handle; |
| 6127 | struct ixgbe_hw *hw = |
| 6128 | IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); |
| 6129 | uint32_t q_idx; |
| 6130 | uint32_t vector_idx = IXGBE_MISC_VEC_ID; |
| 6131 | uint32_t base = IXGBE_MISC_VEC_ID; |
| 6132 | |
| 6133 | /* Configure VF other cause ivar */ |
| 6134 | ixgbevf_set_ivar_map(hw, -1, 1, vector_idx); |
| 6135 | |
| 6136 | /* won't configure msix register if no mapping is done |
| 6137 | * between intr vector and event fd. |
| 6138 | */ |
| 6139 | if (!rte_intr_dp_is_en(intr_handle)) |
| 6140 | return; |
| 6141 | |
| 6142 | if (rte_intr_allow_others(intr_handle)) { |
| 6143 | base = IXGBE_RX_VEC_START; |
| 6144 | vector_idx = IXGBE_RX_VEC_START; |
| 6145 | } |
| 6146 | |
| 6147 | /* Configure all RX queues of VF */ |
| 6148 | for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) { |
| 6149 | /* Force all queue use vector 0, |
| 6150 | * as IXGBE_VF_MAXMSIVECTOR = 1 |
| 6151 | */ |
| 6152 | ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx); |
| 6153 | rte_intr_vec_list_index_set(intr_handle, q_idx, |
| 6154 | vector_idx); |
| 6155 | if (vector_idx < base + rte_intr_nb_efd_get(intr_handle) |
| 6156 | - 1) |
| 6157 | vector_idx++; |
| 6158 | } |
| 6159 | |
| 6160 | /* As RX queue setting above show, all queues use the vector 0. |
| 6161 | * Set only the ITR value of IXGBE_MISC_VEC_ID. |
| 6162 | */ |
| 6163 | IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID), |
| 6164 | IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT) |
| 6165 | | IXGBE_EITR_CNT_WDIS); |
| 6166 | } |
| 6167 | |
| 6168 | /** |
| 6169 | * Sets up the hardware to properly generate MSI-X interrupts |
no test coverage detected