* set the IVAR registers, mapping interrupt causes to vectors * @param hw * pointer to ixgbe_hw struct * @direction * 0 for Rx, 1 for Tx, -1 for other causes * @queue * queue to map the corresponding interrupt to * @msix_vector * the vector to map to the corresponding queue */
| 6082 | * the vector to map to the corresponding queue |
| 6083 | */ |
| 6084 | static void |
| 6085 | ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, |
| 6086 | uint8_t queue, uint8_t msix_vector) |
| 6087 | { |
| 6088 | uint32_t tmp, idx; |
| 6089 | |
| 6090 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; |
| 6091 | if (hw->mac.type == ixgbe_mac_82598EB) { |
| 6092 | if (direction == -1) |
| 6093 | direction = 0; |
| 6094 | idx = (((direction * 64) + queue) >> 2) & 0x1F; |
| 6095 | tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx)); |
| 6096 | tmp &= ~(0xFF << (8 * (queue & 0x3))); |
| 6097 | tmp |= (msix_vector << (8 * (queue & 0x3))); |
| 6098 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp); |
| 6099 | } else if ((hw->mac.type == ixgbe_mac_82599EB) || |
| 6100 | (hw->mac.type == ixgbe_mac_X540) || |
| 6101 | (hw->mac.type == ixgbe_mac_X550) || |
| 6102 | (hw->mac.type == ixgbe_mac_X550EM_a) || |
| 6103 | (hw->mac.type == ixgbe_mac_X550EM_x)) { |
| 6104 | if (direction == -1) { |
| 6105 | /* other causes */ |
| 6106 | idx = ((queue & 1) * 8); |
| 6107 | tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC); |
| 6108 | tmp &= ~(0xFF << idx); |
| 6109 | tmp |= (msix_vector << idx); |
| 6110 | IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp); |
| 6111 | } else { |
| 6112 | /* rx or tx causes */ |
| 6113 | idx = ((16 * (queue & 1)) + (8 * direction)); |
| 6114 | tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); |
| 6115 | tmp &= ~(0xFF << idx); |
| 6116 | tmp |= (msix_vector << idx); |
| 6117 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp); |
| 6118 | } |
| 6119 | } |
| 6120 | } |
| 6121 | |
| 6122 | static void |
| 6123 | ixgbevf_configure_msix(struct rte_eth_dev *dev) |
no outgoing calls
no test coverage detected