* Sets up the hardware to properly generate MSI-X interrupts * @hw * board private structure */
| 6171 | * board private structure |
| 6172 | */ |
| 6173 | static void |
| 6174 | ixgbe_configure_msix(struct rte_eth_dev *dev) |
| 6175 | { |
| 6176 | struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); |
| 6177 | struct rte_intr_handle *intr_handle = pci_dev->intr_handle; |
| 6178 | struct ixgbe_hw *hw = |
| 6179 | IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); |
| 6180 | uint32_t queue_id, base = IXGBE_MISC_VEC_ID; |
| 6181 | uint32_t vec = IXGBE_MISC_VEC_ID; |
| 6182 | uint32_t mask; |
| 6183 | uint32_t gpie; |
| 6184 | |
| 6185 | /* won't configure msix register if no mapping is done |
| 6186 | * between intr vector and event fd |
| 6187 | * but if misx has been enabled already, need to configure |
| 6188 | * auto clean, auto mask and throttling. |
| 6189 | */ |
| 6190 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); |
| 6191 | if (!rte_intr_dp_is_en(intr_handle) && |
| 6192 | !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT))) |
| 6193 | return; |
| 6194 | |
| 6195 | if (rte_intr_allow_others(intr_handle)) |
| 6196 | vec = base = IXGBE_RX_VEC_START; |
| 6197 | |
| 6198 | /* setup GPIE for MSI-x mode */ |
| 6199 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); |
| 6200 | gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | |
| 6201 | IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME; |
| 6202 | /* auto clearing and auto setting corresponding bits in EIMS |
| 6203 | * when MSI-X interrupt is triggered |
| 6204 | */ |
| 6205 | if (hw->mac.type == ixgbe_mac_82598EB) { |
| 6206 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); |
| 6207 | } else { |
| 6208 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); |
| 6209 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); |
| 6210 | } |
| 6211 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); |
| 6212 | |
| 6213 | /* Populate the IVAR table and set the ITR values to the |
| 6214 | * corresponding register. |
| 6215 | */ |
| 6216 | if (rte_intr_dp_is_en(intr_handle)) { |
| 6217 | for (queue_id = 0; queue_id < dev->data->nb_rx_queues; |
| 6218 | queue_id++) { |
| 6219 | /* by default, 1:1 mapping */ |
| 6220 | ixgbe_set_ivar_map(hw, 0, queue_id, vec); |
| 6221 | rte_intr_vec_list_index_set(intr_handle, |
| 6222 | queue_id, vec); |
| 6223 | if (vec < base + rte_intr_nb_efd_get(intr_handle) |
| 6224 | - 1) |
| 6225 | vec++; |
| 6226 | } |
| 6227 | |
| 6228 | switch (hw->mac.type) { |
| 6229 | case ixgbe_mac_82598EB: |
| 6230 | ixgbe_set_ivar_map(hw, -1, |
no test coverage detected