| 3554 | } |
| 3555 | |
| 3556 | void |
| 3557 | ice_vsi_enable_queues_intr(struct ice_vsi *vsi) |
| 3558 | { |
| 3559 | struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id]; |
| 3560 | struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); |
| 3561 | struct rte_intr_handle *intr_handle = pci_dev->intr_handle; |
| 3562 | struct ice_hw *hw = ICE_VSI_TO_HW(vsi); |
| 3563 | uint16_t msix_intr, i; |
| 3564 | |
| 3565 | if (rte_intr_allow_others(intr_handle)) |
| 3566 | for (i = 0; i < vsi->nb_used_qps; i++) { |
| 3567 | msix_intr = vsi->msix_intr + i; |
| 3568 | ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), |
| 3569 | GLINT_DYN_CTL_INTENA_M | |
| 3570 | GLINT_DYN_CTL_CLEARPBA_M | |
| 3571 | GLINT_DYN_CTL_ITR_INDX_M | |
| 3572 | GLINT_DYN_CTL_WB_ON_ITR_M); |
| 3573 | } |
| 3574 | else |
| 3575 | ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), |
| 3576 | GLINT_DYN_CTL_INTENA_M | |
| 3577 | GLINT_DYN_CTL_CLEARPBA_M | |
| 3578 | GLINT_DYN_CTL_ITR_INDX_M | |
| 3579 | GLINT_DYN_CTL_WB_ON_ITR_M); |
| 3580 | } |
| 3581 | |
| 3582 | static int |
| 3583 | ice_rxq_intr_setup(struct rte_eth_dev *dev) |
no test coverage detected