| 3580 | } |
| 3581 | |
| 3582 | static int |
| 3583 | ice_rxq_intr_setup(struct rte_eth_dev *dev) |
| 3584 | { |
| 3585 | struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private); |
| 3586 | struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev); |
| 3587 | struct rte_intr_handle *intr_handle = pci_dev->intr_handle; |
| 3588 | struct ice_vsi *vsi = pf->main_vsi; |
| 3589 | uint32_t intr_vector = 0; |
| 3590 | |
| 3591 | rte_intr_disable(intr_handle); |
| 3592 | |
| 3593 | /* check and configure queue intr-vector mapping */ |
| 3594 | if ((rte_intr_cap_multiple(intr_handle) || |
| 3595 | !RTE_ETH_DEV_SRIOV(dev).active) && |
| 3596 | dev->data->dev_conf.intr_conf.rxq != 0) { |
| 3597 | intr_vector = dev->data->nb_rx_queues; |
| 3598 | if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) { |
| 3599 | PMD_DRV_LOG(ERR, "At most %d intr queues supported", |
| 3600 | ICE_MAX_INTR_QUEUE_NUM); |
| 3601 | return -ENOTSUP; |
| 3602 | } |
| 3603 | if (rte_intr_efd_enable(intr_handle, intr_vector)) |
| 3604 | return -1; |
| 3605 | } |
| 3606 | |
| 3607 | if (rte_intr_dp_is_en(intr_handle)) { |
| 3608 | if (rte_intr_vec_list_alloc(intr_handle, NULL, |
| 3609 | dev->data->nb_rx_queues)) { |
| 3610 | PMD_DRV_LOG(ERR, |
| 3611 | "Failed to allocate %d rx_queues intr_vec", |
| 3612 | dev->data->nb_rx_queues); |
| 3613 | return -ENOMEM; |
| 3614 | } |
| 3615 | } |
| 3616 | |
| 3617 | /* Map queues with MSIX interrupt */ |
| 3618 | vsi->nb_used_qps = dev->data->nb_rx_queues; |
| 3619 | ice_vsi_queues_bind_intr(vsi); |
| 3620 | |
| 3621 | /* Enable interrupts for all the queues */ |
| 3622 | ice_vsi_enable_queues_intr(vsi); |
| 3623 | |
| 3624 | rte_intr_enable(intr_handle); |
| 3625 | |
| 3626 | return 0; |
| 3627 | } |
| 3628 | |
| 3629 | static enum ice_status |
| 3630 | ice_get_link_info_safe(struct ice_pf *pf, bool ena_lse, |
no test coverage detected