| 6384 | } |
| 6385 | |
| 6386 | int |
| 6387 | i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on) |
| 6388 | { |
| 6389 | uint32_t reg; |
| 6390 | uint16_t j; |
| 6391 | |
| 6392 | /* Wait until the request is finished */ |
| 6393 | for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) { |
| 6394 | rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US); |
| 6395 | reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx)); |
| 6396 | if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^ |
| 6397 | ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1)) |
| 6398 | break; |
| 6399 | } |
| 6400 | |
| 6401 | if (on) { |
| 6402 | if (reg & I40E_QRX_ENA_QENA_STAT_MASK) |
| 6403 | return I40E_SUCCESS; /* Already on, skip next steps */ |
| 6404 | reg |= I40E_QRX_ENA_QENA_REQ_MASK; |
| 6405 | } else { |
| 6406 | if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK)) |
| 6407 | return I40E_SUCCESS; /* Already off, skip next steps */ |
| 6408 | reg &= ~I40E_QRX_ENA_QENA_REQ_MASK; |
| 6409 | } |
| 6410 | |
| 6411 | /* Write the register */ |
| 6412 | I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg); |
| 6413 | /* Check the result */ |
| 6414 | for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) { |
| 6415 | rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US); |
| 6416 | reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx)); |
| 6417 | if (on) { |
| 6418 | if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) && |
| 6419 | (reg & I40E_QRX_ENA_QENA_STAT_MASK)) |
| 6420 | break; |
| 6421 | } else { |
| 6422 | if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) && |
| 6423 | !(reg & I40E_QRX_ENA_QENA_STAT_MASK)) |
| 6424 | break; |
| 6425 | } |
| 6426 | } |
| 6427 | |
| 6428 | /* Check if it is timeout */ |
| 6429 | if (j >= I40E_CHK_Q_ENA_COUNT) { |
| 6430 | PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]", |
| 6431 | (on ? "enable" : "disable"), q_idx); |
| 6432 | return I40E_ERR_TIMEOUT; |
| 6433 | } |
| 6434 | |
| 6435 | return I40E_SUCCESS; |
| 6436 | } |
| 6437 | |
| 6438 | /* Initialize VSI for TX */ |
| 6439 | static int |
no outgoing calls
no test coverage detected