| 1313 | } |
| 1314 | |
| 1315 | int |
| 1316 | cpfl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id) |
| 1317 | { |
| 1318 | struct cpfl_vport *cpfl_vport = dev->data->dev_private; |
| 1319 | struct idpf_vport *vport = &cpfl_vport->base; |
| 1320 | struct cpfl_tx_queue *cpfl_txq; |
| 1321 | struct idpf_tx_queue *txq; |
| 1322 | int err; |
| 1323 | |
| 1324 | if (tx_queue_id >= dev->data->nb_tx_queues) |
| 1325 | return -EINVAL; |
| 1326 | |
| 1327 | cpfl_txq = dev->data->tx_queues[tx_queue_id]; |
| 1328 | |
| 1329 | if (cpfl_txq->hairpin_info.hairpin_q) |
| 1330 | err = cpfl_switch_hairpin_rxtx_queue(cpfl_vport, |
| 1331 | tx_queue_id - cpfl_vport->nb_data_txq, |
| 1332 | false, false); |
| 1333 | else |
| 1334 | err = idpf_vc_queue_switch(vport, tx_queue_id, false, false); |
| 1335 | if (err != 0) { |
| 1336 | PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off", |
| 1337 | tx_queue_id); |
| 1338 | return err; |
| 1339 | } |
| 1340 | |
| 1341 | txq = &cpfl_txq->base; |
| 1342 | txq->q_started = false; |
| 1343 | txq->ops->release_mbufs(txq); |
| 1344 | if (vport->txq_model == VIRTCHNL2_QUEUE_MODEL_SINGLE) { |
| 1345 | idpf_qc_single_tx_queue_reset(txq); |
| 1346 | } else { |
| 1347 | if (cpfl_txq->hairpin_info.hairpin_q) { |
| 1348 | cpfl_tx_hairpin_descq_reset(txq); |
| 1349 | cpfl_tx_hairpin_complq_reset(txq->complq); |
| 1350 | } else { |
| 1351 | idpf_qc_split_tx_descq_reset(txq); |
| 1352 | idpf_qc_split_tx_complq_reset(txq->complq); |
| 1353 | } |
| 1354 | } |
| 1355 | |
| 1356 | if (!cpfl_txq->hairpin_info.hairpin_q) |
| 1357 | dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; |
| 1358 | |
| 1359 | return 0; |
| 1360 | } |
| 1361 | |
| 1362 | void |
| 1363 | cpfl_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid) |
no test coverage detected