| 548 | } |
| 549 | |
| 550 | static int bnxt_alloc_rx_agg_ring(struct bnxt *bp, int queue_index) |
| 551 | { |
| 552 | unsigned int map_idx = queue_index + bp->rx_cp_nr_rings; |
| 553 | struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index]; |
| 554 | struct bnxt_cp_ring_info *cpr = rxq->cp_ring; |
| 555 | struct bnxt_ring *cp_ring = cpr->cp_ring_struct; |
| 556 | struct bnxt_rx_ring_info *rxr = rxq->rx_ring; |
| 557 | struct bnxt_ring *ring = rxr->ag_ring_struct; |
| 558 | uint32_t hw_stats_ctx_id = HWRM_NA_SIGNATURE; |
| 559 | uint8_t ring_type; |
| 560 | int rc = 0; |
| 561 | |
| 562 | if (!bnxt_need_agg_ring(bp->eth_dev)) |
| 563 | return 0; |
| 564 | |
| 565 | ring->fw_rx_ring_id = rxr->rx_ring_struct->fw_ring_id; |
| 566 | |
| 567 | if (BNXT_CHIP_P5(bp)) { |
| 568 | ring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG; |
| 569 | hw_stats_ctx_id = cpr->hw_stats_ctx_id; |
| 570 | } else { |
| 571 | ring_type = HWRM_RING_ALLOC_INPUT_RING_TYPE_RX; |
| 572 | } |
| 573 | |
| 574 | rc = bnxt_hwrm_ring_alloc(bp, ring, ring_type, map_idx, |
| 575 | hw_stats_ctx_id, cp_ring->fw_ring_id, 0); |
| 576 | |
| 577 | if (rc) |
| 578 | return rc; |
| 579 | |
| 580 | rxr->ag_raw_prod = 0; |
| 581 | if (BNXT_HAS_RING_GRPS(bp)) |
| 582 | bp->grp_info[queue_index].ag_fw_ring_id = ring->fw_ring_id; |
| 583 | bnxt_set_db(bp, &rxr->ag_db, ring_type, map_idx, ring->fw_ring_id, |
| 584 | ring->ring_mask); |
| 585 | bnxt_db_write(&rxr->ag_db, rxr->ag_raw_prod); |
| 586 | |
| 587 | return 0; |
| 588 | } |
| 589 | |
| 590 | int bnxt_alloc_hwrm_rx_ring(struct bnxt *bp, int queue_index) |
| 591 | { |
no test coverage detected