| 1660 | } |
| 1661 | |
| 1662 | int bnxt_hwrm_ring_alloc(struct bnxt *bp, |
| 1663 | struct bnxt_ring *ring, |
| 1664 | uint32_t ring_type, uint32_t map_index, |
| 1665 | uint32_t stats_ctx_id, uint32_t cmpl_ring_id, |
| 1666 | uint16_t tx_cosq_id) |
| 1667 | { |
| 1668 | int rc = 0; |
| 1669 | uint32_t enables = 0; |
| 1670 | struct hwrm_ring_alloc_input req = {.req_type = 0 }; |
| 1671 | struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr; |
| 1672 | struct rte_mempool *mb_pool; |
| 1673 | uint16_t rx_buf_size; |
| 1674 | |
| 1675 | HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB); |
| 1676 | |
| 1677 | req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma); |
| 1678 | req.fbo = rte_cpu_to_le_32(0); |
| 1679 | /* Association of ring index with doorbell index */ |
| 1680 | req.logical_id = rte_cpu_to_le_16(map_index); |
| 1681 | req.length = rte_cpu_to_le_32(ring->ring_size); |
| 1682 | |
| 1683 | switch (ring_type) { |
| 1684 | case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX: |
| 1685 | req.ring_type = ring_type; |
| 1686 | req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id); |
| 1687 | req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id); |
| 1688 | req.queue_id = rte_cpu_to_le_16(tx_cosq_id); |
| 1689 | if (stats_ctx_id != INVALID_STATS_CTX_ID) |
| 1690 | enables |= |
| 1691 | HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID; |
| 1692 | break; |
| 1693 | case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX: |
| 1694 | req.ring_type = ring_type; |
| 1695 | req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id); |
| 1696 | req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id); |
| 1697 | if (BNXT_CHIP_P5(bp)) { |
| 1698 | mb_pool = bp->rx_queues[0]->mb_pool; |
| 1699 | rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) - |
| 1700 | RTE_PKTMBUF_HEADROOM; |
| 1701 | rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size); |
| 1702 | req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size); |
| 1703 | enables |= |
| 1704 | HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID; |
| 1705 | } |
| 1706 | if (stats_ctx_id != INVALID_STATS_CTX_ID) |
| 1707 | enables |= |
| 1708 | HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID; |
| 1709 | break; |
| 1710 | case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL: |
| 1711 | req.ring_type = ring_type; |
| 1712 | if (BNXT_HAS_NQ(bp)) { |
| 1713 | /* Association of cp ring with nq */ |
| 1714 | req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id); |
| 1715 | enables |= |
| 1716 | HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID; |
| 1717 | } |
| 1718 | req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX; |
| 1719 | break; |
no test coverage detected