| 3412 | } |
| 3413 | |
| 3414 | static inline int |
| 3415 | dlb2_process_dequeue_four_qes(struct dlb2_eventdev_port *ev_port, |
| 3416 | struct dlb2_port *qm_port, |
| 3417 | struct rte_event *events, |
| 3418 | struct dlb2_dequeue_qe *qes) |
| 3419 | { |
| 3420 | int sched_type_map[] = { |
| 3421 | [DLB2_SCHED_ATOMIC] = RTE_SCHED_TYPE_ATOMIC, |
| 3422 | [DLB2_SCHED_UNORDERED] = RTE_SCHED_TYPE_PARALLEL, |
| 3423 | [DLB2_SCHED_ORDERED] = RTE_SCHED_TYPE_ORDERED, |
| 3424 | [DLB2_SCHED_DIRECTED] = RTE_SCHED_TYPE_ATOMIC, |
| 3425 | }; |
| 3426 | const int num_events = DLB2_NUM_QES_PER_CACHE_LINE; |
| 3427 | uint8_t *qid_mappings = qm_port->qid_mappings; |
| 3428 | __m128i sse_evt[2]; |
| 3429 | |
| 3430 | /* In the unlikely case that any of the QE error bits are set, process |
| 3431 | * them one at a time. |
| 3432 | */ |
| 3433 | if (unlikely(qes[0].error || qes[1].error || |
| 3434 | qes[2].error || qes[3].error)) |
| 3435 | return dlb2_process_dequeue_qes(ev_port, qm_port, events, |
| 3436 | qes, num_events); |
| 3437 | |
| 3438 | events[0].u64 = qes[0].data; |
| 3439 | events[1].u64 = qes[1].data; |
| 3440 | events[2].u64 = qes[2].data; |
| 3441 | events[3].u64 = qes[3].data; |
| 3442 | |
| 3443 | /* Construct the metadata portion of two struct rte_events |
| 3444 | * in one 128b SSE register. Event metadata is constructed in the SSE |
| 3445 | * registers like so: |
| 3446 | * sse_evt[0][63:0]: event[0]'s metadata |
| 3447 | * sse_evt[0][127:64]: event[1]'s metadata |
| 3448 | * sse_evt[1][63:0]: event[2]'s metadata |
| 3449 | * sse_evt[1][127:64]: event[3]'s metadata |
| 3450 | */ |
| 3451 | sse_evt[0] = _mm_setzero_si128(); |
| 3452 | sse_evt[1] = _mm_setzero_si128(); |
| 3453 | |
| 3454 | /* Convert the hardware queue ID to an event queue ID and store it in |
| 3455 | * the metadata: |
| 3456 | * sse_evt[0][47:40] = qid_mappings[qes[0].qid] |
| 3457 | * sse_evt[0][111:104] = qid_mappings[qes[1].qid] |
| 3458 | * sse_evt[1][47:40] = qid_mappings[qes[2].qid] |
| 3459 | * sse_evt[1][111:104] = qid_mappings[qes[3].qid] |
| 3460 | */ |
| 3461 | #define DLB_EVENT_QUEUE_ID_BYTE 5 |
| 3462 | sse_evt[0] = _mm_insert_epi8(sse_evt[0], |
| 3463 | qid_mappings[qes[0].qid], |
| 3464 | DLB_EVENT_QUEUE_ID_BYTE); |
| 3465 | sse_evt[0] = _mm_insert_epi8(sse_evt[0], |
| 3466 | qid_mappings[qes[1].qid], |
| 3467 | DLB_EVENT_QUEUE_ID_BYTE + 8); |
| 3468 | sse_evt[1] = _mm_insert_epi8(sse_evt[1], |
| 3469 | qid_mappings[qes[2].qid], |
| 3470 | DLB_EVENT_QUEUE_ID_BYTE); |
| 3471 | sse_evt[1] = _mm_insert_epi8(sse_evt[1], |
no test coverage detected