Function dlb2_dequeue_wait

dpdk/drivers/event/dlb2/dlb2.c:3293–3354

}

static inline int
dlb2_dequeue_wait(struct dlb2_eventdev *dlb2,
		  struct dlb2_eventdev_port *ev_port,
		  struct dlb2_port *qm_port,
		  uint64_t timeout,
		  uint64_t start_ticks)
{
	struct process_local_port_data *port_data;
	uint64_t elapsed_ticks;

	port_data = &dlb2_port[qm_port->id][PORT_TYPE(qm_port)];

	elapsed_ticks = rte_get_timer_cycles() - start_ticks;

	/* Wait/poll time expired */
	if (elapsed_ticks >= timeout) {
		return 1;
	} else if (dlb2->umwait_allowed) {
		struct rte_power_monitor_cond pmc;
		volatile struct dlb2_dequeue_qe *cq_base;
		union {
			uint64_t raw_qe[2];
			struct dlb2_dequeue_qe qe;
		} qe_mask;
		uint64_t expected_value;
		volatile uint64_t *monitor_addr;

		qe_mask.qe.cq_gen = 1; /* set mask */

		cq_base = port_data->cq_base;
		monitor_addr = (volatile uint64_t *)(volatile void *)
			&cq_base[qm_port->cq_idx];
		monitor_addr++; /* cq_gen bit is in second 64bit location */

		if (qm_port->gen_bit)
			expected_value = qe_mask.raw_qe[1];
		else
			expected_value = 0;

		pmc.addr = monitor_addr;
		/* store expected value and comparison mask in opaque data */
		pmc.opaque[CLB_VAL_IDX] = expected_value;
		pmc.opaque[CLB_MASK_IDX] = qe_mask.raw_qe[1];
		/* set up callback */
		pmc.fn = dlb2_monitor_callback;
		pmc.size = sizeof(uint64_t);

		rte_power_monitor(&pmc, timeout + start_ticks);

		DLB2_INC_STAT(ev_port->stats.traffic.rx_umonitor_umwait, 1);
	} else {
		uint64_t poll_interval = dlb2->poll_interval;
		uint64_t curr_ticks = rte_get_timer_cycles();
		uint64_t init_ticks = curr_ticks;

		while ((curr_ticks - start_ticks < timeout) &&
		       (curr_ticks - init_ticks < poll_interval))
			curr_ticks = rte_get_timer_cycles();