IMemoryUnit

ADC A, (HL) - 0x8E The contents specified by the address of the HL register pair and the contents of the carry flag are added to the contents

ADC A, n - 0xCE The 8-bit n operand, along with the carry flag, is added to the contents of the accumulator, and the result is stored in the

ADC A, r 10001rrr The contents of the r register, and the contents of the carry flag, are added to the contents of the accumulator, and t

ADD A, (HL) - 0x86 The byte at the memory address specified by the contents of the HL register pair is added to the contents of the accumulat

ADD A, n - 0xC6 The integer n is added to the contents of the accumulator, and the reults are stored in the accumulator. 8 Cycles F

ADD A, r 10000rrr The contents of the r register are added to the contents of the accumulator, and the result is stored in the accumulato

ADD HL, ss 00ss1001 The contents of the register pair ss (BC, DE, HL, SP) are added to the contents of the register pair HL and the resul

ADD SP, dd 0xE8 16 Cycles Flags affected(znhc): 00hc */

AND (HL) - 0xA6 The logical AND operation is performed between the byte contained at the memory address specified by the HL register and the

AND n 11100110 (0xE6) The logical AND operation is performed between the byte specified in n and the byte contained in the accumulator. T

AND r 10100rrr The logical AND operation is performed between the register specified in the r operand and the byte contained in the accum

BIT b, (HL) 12 Cycles Flags affected(znhc): z01- */

BIT b, r 11001011 01bbbrrr This instruction tests bit b in register r and sets the Z flag accordingly. 8 Cycles Flags affected(znhc

CALL cc, nn 11ccc100 000 NZ 001 Z 010 NC 011 C 24 Cycles if taken 12 Cycles if not taken Flags affected(znhc): ----

CALL nn - 0xCD Pushes the PC to the SP, then sets the PC to the target address(nn). 24 Cycles Flags affected(znhc): ---- */

CCF - 0x3F Toggle the carry flag. 4 Cycles Flags affected(znhc): -00c */

CPL - 0x2F The contents of the accumulator are inverted. 4 Cycles Flags affected(znhc): -11- */

CP (HL) - 0xBE The contents of 8-bit register HL are compared with the contents of the accumulator. If there is a true compare, the Z flag is

CP n - 0xFE The contents of 8-bit operand n are compared with the contents of the accumulator. If there is a true compare, the Z flag is set.

CP r 10111rrr The contents of 8-bit register r are compared with the contents of the accumulator. If there is a true compare, the Z flag

DAA - 0x27 This instruction conditionally adjust the accumulator for BCD addition and subtraction operations. For addition (ADD, ADC, INC) or

DEC (hl) - 0x35 The byte at the address (HL) is decremented. 12 Cycles Flags affected(znhc): z1h- */

DEC r 00rrr101 Register r is decremented, where r identifies register A, B, C, D, E, H, or L. 4 Cycles Flags affected(znhc): z1h- *

DEC rr 00rr1011 16-bit register rr is decremented, where rr identifies register pairs BC, DE, HL, or SP. 8 Cycles Flags affected(zn

DI - 0xF3 Disable interrupts 4 Cycles Flags affected(znhc): ---- */

EI - 0xFB Enable interrupts 4 Cycles Flags affected(znhc): ---- */

HALT - 0x76 0 Cycles Flags affected(znhc): ---- */

INC (HL) - 0x34 The byte at the address (HL) is incremented. 12 Cycles Flags affected(znhc): z0h- */

INC r 00rrr100 Register r is incremented, where r identifies register A, B, C, D, E, H, or L. 4 Cycles Flags affected(znhc): z0h- *

INC rr 00rr0011 16-bit register rr is incremented, where rr identifies register pairs BC, DE, HL, or SP. 8 Cycles Flags affected(zn

JP HL - 0xE9 The PC is loaded with the value of HL. 4 Cycles Flags affected(znhc): ---- */

JP cc, nn 11ccc010 000 NZ 001 Z 010 NC 011 C 16 Cycles if taken 12 Cycles if not taken Flags affected(znhc): ---- *

JP nn - 0xC3 Jump to nn 16 Cycles Flags affected(znhc): ---- */