A timing constraint between commands at a specific hierarchy level. The latency is an expression string using timing parameter names, e.g. "n

Descriptor for a typed component parameter. Usage in a Component subclass: clock_ratio = Param(int, required=True) ipc = Param(in

Slot for a sub-component. config_key is the key name used in the C++ config dict. Usage in a Component subclass: translation = Child

Slot for a list of sub-components of the same interface type. Usage in a Component subclass: controllers = ChildList("controller")

What the device would say about ``command`` at a given clock cycle. Fields: preq: The prerequisite command the device wants next. Equals

Theoretical targets and timing constants derived from a testcase dict.

Manage a Nuxt visualizer server subprocess. Parameters ---------- port : int TCP port for the Nuxt server (default from env or 30

All-bank refresh — issues one REFab per standard-defined scope node every nREFI cycles.

AttackThrottler Per-(thread_id, bank_id) ACT counter, with N rotating maps. update() rotates by clearing the active map and advancing the active idx e

BHO3 — BlockHammer-extended OoO frontend (see bhO3.cpp). The class declaration lives in this header so the BlockHammer controller can dynamic_cast<BHO

BHO3Core — same simplified out-of-order pipeline as SimpleO3Core, but holds a pointer to BHO3LLC instead of SimpleO3LLC so the LLC's blacklist API is

BHO3LLC — SimpleO3LLC equivalent extended with a per-core MSHR-blacklist API. The BlockHammer controller calls add_blacklist(source_id) and set_blackl

Bank-targeting pattern for command state dispatch

Records every DRAM command to a binary SoA trace file (RAM2BIN v1). Buffers per-field arrays during simulation and flushes them in Structure-of-Array

Channel-Rank-BankGroup-Bank-Row-Column (MSB to LSB)

Closed row policy with CAP — close rows after N column accesses. After CAP is reached, the policy opportunistically rewrites RD → RDA / WR → WRA (aut

Records every DRAM command issued by the controller to a trace file. Two output modes: - **Text** (default): CSV with a self-documenting header line.

Counts specified DRAM commands and writes totals to a CSV file at finalization. Example config (Python): ramulator.ControllerPlugin.CommandCounter( c

Base class for Ramulator components. Subclasses define their configuration schema via Param and Child class attributes. Instances hold concre

Shared infrastructure for all DRAM controller implementations. Provides buffers, stats, sub-component management, and low-level scheduling helpers. Su

DDR5 with both RFMab (controller-visible JEDEC layer) and VRR (used by in-DRAM TRR plugins to model the victim refresh that happens inside the

Meta information about a command

* @brief DRAM Device — owns the DRAMSpec, node tree, and flat bank array. * * Provides all device-level operations: command issue (timing + state

* @brief DRAM Device Node — represents one level in the DRAM hierarchy * * DRAMNode holds per-node state (m_state, m_row_state, timing history).

Forward declaration — full definition in node.h

Runtime representation of a DRAM standard's specification. Base class for concrete standards (e.g., DDR4) which self-populate in their constructor fro

Forward reference — DRAMSpec is defined in dram_spec.h, included by each standard header before this file.

Base class for all DRAM standards. Subclasses declare structure as class attributes (read by codegen) and presets for runtime config (read by

Thin Python wrapper over the C++ ``_DeviceUnderTest`` shim. Holds DRAM metadata (``timings``, ``level_names``, ...) and exposes ``probe`` / `