Issue ACT to two banks, then RD on a0 at the earliest cycle both ACTs allow. Returns the column command issue cycle.

Yield all source files under src_dir.

Return the first cycle at or after ``start`` where ``command`` is ready.

HBM4 32Gb 8Hi @ 8000Mbps. Override via kwargs (e.g. nFAW=60).

Run the simulation to completion.

Gracefully stop the server subprocess.

Apply immediately (not in nextTick) so the next regl frame sees the new window — deferred updates looked like “constant had no effect”.

Calls setup() on m_impl first, then on all gathered child components. Important: setup() implementations must NOT recursively call children's setup().

Calls setup() on m_impl first, then on all gathered child components. Important: setup() implementations must NOT recursively call children's setup().

Bytes per DRAM transaction. Some standards transfer non-payload metadata bits on the wire, so a payload override can differ from the physical width.

Issue a priority ACT + RD/WR pair targeting the RCT row.

Build a Request from an address vector, setting the flat address for write-forwarding.

Scan a file for RAMULATOR_CREATE_CHILD, RAMULATOR_CREATE_CHILD_LIST, and RAMULATOR_CHILD comment markers. Returns list of dicts: [{"config_ke

Scan a file for RAMULATOR_PARSE_PARAM calls. Returns list of {name, cpp_type, required, default_val}.

Block until the user presses Ctrl+C, then stop the server.

Build the figure with the lat-tp curves and basic axis styling.

Evaluate 'nCL + nBL + 2 - nCWL' using resolved timing values.

Collect all Param, Child, and ChildList descriptors from the class hierarchy.

Compare measured unloaded latency vs theoretical. Theoretical unloaded latency for a random (row-miss) probe: (nRP + nRCD + nCL) * tCK_ns

Convert raw sweep results into per-read-ratio lat-tp curves. Returns: { read_ratio: { "throughput": [float, ...], # GB/s, so

Extract DRAM hierarchy layout for LatencyThroughputTrace address generation. Takes a Python DRAM spec object and returns a dict of kwargs to pass