| 123 | } |
| 124 | |
| 125 | static bool uart_receive_char() { |
| 126 | uart_transfer_t transfer; |
| 127 | if (!uart.receive_char(&transfer)) { |
| 128 | /* RX timeout not reset*/ |
| 129 | return false; |
| 130 | } |
| 131 | |
| 132 | uint8_t stat = 0; |
| 133 | if (unlikely(transfer.divisor != uart.divisor)) { |
| 134 | /* Frame error */ |
| 135 | stat = 1 << 3; |
| 136 | } else { |
| 137 | uint8_t lcrDiff = uart.lcr & (UART_LCR_CHAR_LEN | UART_LCR_STOP_BITS | UART_LCR_PARITY_ENABLE | UART_LCR_PARITY_EVEN | UART_LCR_PARITY_STICK); |
| 138 | lcrDiff ^= transfer.lcr; |
| 139 | if (unlikely(lcrDiff)) { |
| 140 | if (lcrDiff & UART_LCR_BREAK) { |
| 141 | /* Break/frame error */ |
| 142 | transfer.ch = 0; |
| 143 | stat = 1 << 4 | 1 << 3; |
| 144 | } else if (lcrDiff & (UART_LCR_CHAR_LEN | UART_LCR_STOP_BITS | UART_LCR_PARITY_ENABLE)) { |
| 145 | /* Frame error */ |
| 146 | stat = 1 << 3; |
| 147 | } else if (transfer.lcr & UART_LCR_PARITY_ENABLE) { |
| 148 | bool parityDiff = lcrDiff & UART_LCR_PARITY_EVEN; |
| 149 | if (lcrDiff & UART_LCR_PARITY_STICK) { |
| 150 | parityDiff ^= bit_parity(transfer.ch); |
| 151 | } |
| 152 | /* Parity error */ |
| 153 | stat = parityDiff << 2; |
| 154 | } |
| 155 | } |
| 156 | } |
| 157 | |
| 158 | size_t index = (uart.rfvi + uart.rfve) & (UART_FIFO_DEPTH - 1); |
| 159 | if (uart_fifo_enabled()) { |
| 160 | /* When FIFO is enabled, received bytes are discarded on overrun */ |
| 161 | if (uart.rfve == UART_FIFO_DEPTH) { |
| 162 | /* Overrun error */ |
| 163 | uart.lsr |= 1 << 1; |
| 164 | uart.isr |= 1 << 2; |
| 165 | /* RX timeout not reset*/ |
| 166 | return false; |
| 167 | } |
| 168 | /* Write new data into the FIFO */ |
| 169 | uart.rxfifo[index] = transfer.ch; |
| 170 | uart.rxstat[index] = stat; |
| 171 | /* On error, track the error count and set the FIFO error bit */ |
| 172 | if (stat) { |
| 173 | uart.rxstatCount++; |
| 174 | uart.lsr |= 1 << 7; |
| 175 | } |
| 176 | /* Restart the timeout counter if not timed out */ |
| 177 | if (!uart.rxTimeoutChars) { |
| 178 | uart.rxTimeoutChars = UART_RX_TIMEOUT_DELAY; |
| 179 | } |
| 180 | } else { |
| 181 | /* When FIFO is disabled, holding register is unconditionally overwritten */ |
| 182 | uart.rxfifo[index] = transfer.ch; |
no test coverage detected