| 219 | } |
| 220 | |
| 221 | static void uart_event(enum sched_item_id id) { |
| 222 | if (uart.txActive) { |
| 223 | /* Finish transmit of current byte */ |
| 224 | uart_transfer_t transfer = { |
| 225 | .ch = uart.tsr, |
| 226 | .lcr = uart.lcr, |
| 227 | .divisor = uart.divisor |
| 228 | }; |
| 229 | uart.transmit_char(&transfer); |
| 230 | |
| 231 | /* Transmit next byte or stop */ |
| 232 | if (likely(uart.tfve)) { |
| 233 | uart_next_transmit(); |
| 234 | } else { |
| 235 | uart.txActive = false; |
| 236 | /* Indicate empty FIFO and empty shift register */ |
| 237 | uart.lsr |= 1 << 6; |
| 238 | } |
| 239 | } |
| 240 | |
| 241 | if (!uart_receive_char() && uart.rxTimeoutChars) { |
| 242 | /* Set the timeout flag if the count expired */ |
| 243 | uart.rxTimeout = (--uart.rxTimeoutChars == 0); |
| 244 | } |
| 245 | |
| 246 | /* Update RX FIFO interrupt based on new fill level and timeout */ |
| 247 | uart_update_rxfifo_trigger(); |
| 248 | intrpt_set(INT_UART, uart.ier & uart.isr); |
| 249 | |
| 250 | if (uart_timer_should_run()) { |
| 251 | sched_repeat(id, uart_char_ticks()); |
| 252 | } |
| 253 | } |
| 254 | |
| 255 | /* Read from the 0xE000 range of ports */ |
| 256 | static uint8_t uart_read(const uint16_t pio, bool peek) { |
nothing calls this directly
no test coverage detected